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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2022-04-07 09:16:32 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-04 13:20:56 +0000 |
| commit | 491f66ee5984201a2b0face10ce2373f2c7f8ace (patch) | |
| tree | 3dfc2df65b846bbcfb99b544e6fd895af559e915 /src/soc/intel/xeon_sp/romstage.c | |
| parent | 5ab991d0ab285ee778ebc3d64875bb73e8c4c78b (diff) | |
| download | coreboot-491f66ee5984201a2b0face10ce2373f2c7f8ace.tar.gz coreboot-491f66ee5984201a2b0face10ce2373f2c7f8ace.tar.bz2 coreboot-491f66ee5984201a2b0face10ce2373f2c7f8ace.zip | |
soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may
contain several warnings/errors related to core, uncore and memory, etc.
mainboard can override it in its romstage.c for its own
Enhanced Warning Log check.
Change-Id: I6f542e71d20307397c398fd757d9408438f681ed
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69143
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/romstage.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/romstage.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index b1c7b3b4036e..d001d61eceaf 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -15,6 +15,7 @@ void mainboard_romstage_entry(void) fsp_memory_init(false); printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n"); + mainboard_ewl_check(); unlock_pam_regions(); @@ -31,3 +32,4 @@ __weak void mainboard_rtc_failed(void) } __weak void save_dimm_info(void) { } +__weak void mainboard_ewl_check(void) { } |