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| author | Naresh Solanki <naresh.solanki@9elements.com> | 2023-10-06 14:35:58 +0200 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2023-12-26 16:51:44 +0000 |
| commit | 93ffdee5ed1e6ffc2c2f16d0b53a95c2b8b8d57b (patch) | |
| tree | 179845e2a212cd8679b23e7ed4bd8ab3dadf1cf8 /src/soc/intel/xeon_sp/spr/romstage.c | |
| parent | 8ed0cd0acc788f37ebfd47980843f1f39efe2581 (diff) | |
| download | coreboot-93ffdee5ed1e6ffc2c2f16d0b53a95c2b8b8d57b.tar.gz coreboot-93ffdee5ed1e6ffc2c2f16d0b53a95c2b8b8d57b.tar.bz2 coreboot-93ffdee5ed1e6ffc2c2f16d0b53a95c2b8b8d57b.zip | |
soc/intel/xeon/spr: Enforce POR frequency setting
For RMT build, add kconfig option to enforce Plan Of Record
restriction on DDR5 frequency & voltage settings.
Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/spr/romstage.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 2b377a4d6b9c..4cce21f24967 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -279,7 +279,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.serialDebugMsgLvl = 0x3; mupd->FspmConfig.AllowedSocketsInParallel = 0x1; mupd->FspmConfig.EnforcePopulationPor = 0x1; - mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; + if (CONFIG(RMT_MEM_POR_FREQ)) + mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; } /* SPR-FSP has no UPD to disable HDA, so do it manually here... */ |