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| author | Hung-Te Lin <hungte@chromium.org> | 2019-08-07 10:15:48 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2019-08-15 00:09:06 +0000 |
| commit | 3b217d5c69de950fde7a15e0c3c109b40f64a9c4 (patch) | |
| tree | aecec7f685292ad8cb1ea263966083301aea835d /src/soc/mediatek/mt8173 | |
| parent | ff0945e8ec8162d463ee017a86d1423dc51dd633 (diff) | |
| download | coreboot-3b217d5c69de950fde7a15e0c3c109b40f64a9c4.tar.gz coreboot-3b217d5c69de950fde7a15e0c3c109b40f64a9c4.tar.bz2 coreboot-3b217d5c69de950fde7a15e0c3c109b40f64a9c4.zip | |
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be
ignored on 8173 because of fixed values in PHY but should be calculated
for newer platforms like 8183.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8173')
| -rw-r--r-- | src/soc/mediatek/mt8173/dsi.c | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/dsi.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index 32f4f1ce1c80..b6ff0bc51f9c 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -122,6 +122,8 @@ void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) timing->da_hs_sync = 0; timing->clk_hs_exit = 2 * lpx; + + timing->d_phy = 12; } void mtk_dsi_pin_drv_ctrl(void) diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 99c51e62ffdd..43cbdcb90957 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -22,6 +22,7 @@ #define MTK_DSI_MIPI_RATIO_NUMERATOR 102 #define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 #define MTK_DSI_DATA_RATE_MIN_MHZ 50 +#define PIXEL_STREAM_CUSTOM_HEADER 0 /* MIPITX is SOC specific and cannot live in common. */ |