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| author | Yu-Ping Wu <yupingso@chromium.org> | 2019-10-24 15:51:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-28 11:58:24 +0000 |
| commit | 947916eb2d2648c1cf605a6c660b705876835ea5 (patch) | |
| tree | 651cc1cc827091b621338f729c21773627d42645 /src/soc/mediatek/mt8183/dramc_init_setting.c | |
| parent | 845652b8bbaeca8373bcf574e12e7d4e406b72e9 (diff) | |
| download | coreboot-947916eb2d2648c1cf605a6c660b705876835ea5.tar.gz coreboot-947916eb2d2648c1cf605a6c660b705876835ea5.tar.bz2 coreboot-947916eb2d2648c1cf605a6c660b705876835ea5.zip | |
soc/mediatek/mt8183: Pass MR values as function arguments
To make data flow more explicit, global variables 'MR01Value' and
'MR13Value' are replaced with local variables, which are passed as
function arguments.
BRANCH=kukui
BUG=none
TEST=1. emerge-kukui coreboot
2. Fast calibration succeeded
Change-Id: Id21483092c86c3ae7dbb1173a2b943defe41a379
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_init_setting.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_init_setting.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 7c95c21da437..2a36b48d5db1 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -739,24 +739,24 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank) return 0; } -u8 MR01Value[FSP_MAX] = {0x26, 0x56}; -u8 MR13Value = (1 << 4) | (1 << 3); -static void dramc_mode_reg_init(u8 freq_group) +static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) { + u8 *MR01Value = mr->MR01Value; u8 MR02Value[FSP_MAX] = {0x12, 0x12}; u8 MR03Value = 0x30; u8 MR11Value[FSP_MAX] = {0x0, 0x23}; u8 MR12Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { {{0x5d, 0x5d}, {0x5d, 0x5d} }, {{0x5d, 0x5d}, {0x5d, 0x5d} }, }; + u8 MR13Value; u8 MR14Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { {{0x5d, 0x10}, {0x5d, 0x10} }, {{0x5d, 0x10}, {0x5d, 0x10} }, }; u8 MR22Value[FSP_MAX] = {0x38, 0x34}; - MR01Value[FSP_0] &= 0x8f; - MR01Value[FSP_1] &= 0x8f; + MR01Value[FSP_0] = 0x6; + MR01Value[FSP_1] = 0x6; if (freq_group == LP4X_DDR1600) { MR02Value[0] = 0x12; @@ -838,6 +838,8 @@ static void dramc_mode_reg_init(u8 freq_group) (2 << 0) | (MR02Value[operate_fsp] << 16)); } + mr->MR13Value = MR13Value; + clrsetbits_le32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24); clrsetbits_le32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24); dramc_set_broadcast(broadcast_bak); @@ -1730,13 +1732,13 @@ static void ddr_update_ac_timing(u8 freq_group) } void dramc_init(const struct sdram_params *params, u8 freq_group, - const struct dram_impedance *impedance) + struct dram_shared_data *shared) { - dramc_setting(params, freq_group, impedance); + dramc_setting(params, freq_group, &shared->impedance); dramc_duty_calibration(params, freq_group); dvfs_settings(freq_group); - dramc_mode_reg_init(freq_group); + dramc_mode_reg_init(freq_group, &shared->mr); ddr_update_ac_timing(freq_group); } |