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path: root/src/soc/mediatek/mt8183/dramc_init_setting.c
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* soc/mediatek/mt8183: Support byte mode and single rank DDRShaoming Chen2021-01-151-76/+312
* soc/mediatek/mt8183: Enable CA perbit mechanismHuayang Duan2020-09-251-19/+27
* soc/mediatek/mt8183: Add ddr geometry to support 6GB, 8GB DDR bootupHuayang Duan2020-08-061-0/+1
* soc/mediatek/mt8183: Add missing register settings for channelsHuayang Duan2020-08-061-13/+18
* soc/mediatek/mt8183: Set CA and DQ vref range to correct valueHuayang Duan2020-05-201-2/+5
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/mediatek: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner2019-12-041-489/+489
* soc/mediatek/mt8183: Pass MR values as function argumentsYu-Ping Wu2019-10-281-8/+10
* soc/mediatek/mt8183: Pass impedance data as a function argumentYu-Ping Wu2019-10-181-5/+6
* soc/mediatek/mt8183: Run calibration with multiple frequencies for DVFS switchHuayang Duan2019-10-181-4/+40
* soc/mediatek/mt8183: Remove unnecessary DRAM register settingsYu-Ping Wu2019-10-171-12/+5
* soc/mediatek/mt8183: Fix DDR phy config numberYu-Ping Wu2019-10-171-2/+2
* soc/mediatek/mt8183: Refactor DRAM init by bit fields APIHung-Te Lin2019-10-171-11/+9
* soc/mediatek/mt8183: Improve code formattingYu-Ping Wu2019-10-171-57/+33
* soc/mediatek/mt8183: Use cached calibration result for faster bootupHuayang Duan2019-10-091-0/+16
* mediatek/mt8183: Implement the dramc init settingHuayang Duan2019-09-201-1067/+1691
* mediatek/mt8183: fix mode register setting fail issueHuayang Duan2019-06-211-45/+129
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-041-1/+1
* mediatek/mt8183: Initialize DRAM with a sequence in constant arrayHuayang Duan2018-10-241-0/+1014
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