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| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2020-06-19 15:28:55 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-10-08 11:58:42 +0000 |
| commit | 86b3bf10e60c137b01b81a37ce9827757f6af42d (patch) | |
| tree | ea5e759fc4615a2629fac4c85503510c77b63cd0 /src/soc/mediatek/mt8183 | |
| parent | 83b33f62cf7b125b524b2fbdea5bd8317be0c154 (diff) | |
| download | coreboot-86b3bf10e60c137b01b81a37ce9827757f6af42d.tar.gz coreboot-86b3bf10e60c137b01b81a37ce9827757f6af42d.tar.bz2 coreboot-86b3bf10e60c137b01b81a37ce9827757f6af42d.zip | |
soc/mediatek: Add function to raise the CPU frequency of MT8192
Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq().
Implement mt_pll_raise_little_cpu_freq() in MT8192.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8183')
| -rw-r--r-- | src/soc/mediatek/mt8183/pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 4570269421d0..0e96f4cc6807 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -362,7 +362,7 @@ void mt_pll_init(void) setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } -void mt_pll_raise_ca53_freq(u32 freq) +void mt_pll_raise_little_cpu_freq(u32 freq) { /* enable [4] intermediate clock armpll_divider_pll1_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); |