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| author | Yidi Lin <yidi.lin@mediatek.com> | 2021-01-07 20:25:54 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-04-13 06:07:54 +0000 |
| commit | 24ea3f3364711f352a8a174e6fc0f22885725ed5 (patch) | |
| tree | 4f055221846c974ec16c5d4aa7f7838cfe1ce55e /src/soc/mediatek/mt8195/include/soc/pll.h | |
| parent | 2bb361f0f5151f0cbf0bfcde085c05ca38c42de9 (diff) | |
| download | coreboot-24ea3f3364711f352a8a174e6fc0f22885725ed5.tar.gz coreboot-24ea3f3364711f352a8a174e6fc0f22885725ed5.tar.bz2 coreboot-24ea3f3364711f352a8a174e6fc0f22885725ed5.zip | |
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC
TEST=boot from SPI-NOR and show console message at bootblock stage.
Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/include/soc/pll.h')
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/pll.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h new file mode 100644 index 000000000000..b8a36fd1ec47 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/pll.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_PLL_H +#define SOC_MEDIATEK_MT8195_PLL_H + +#include <soc/pll_common.h> + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, +}; + +/* top_mux rate */ +enum { + UART_HZ = CLK26M_HZ, +}; + +#endif /* SOC_MEDIATEK_MT8195_PLL_H */ |