src/soc/mediatek/mt8195/include/soc/pll.h


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/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef SOC_MEDIATEK_MT8195_PLL_H
#define SOC_MEDIATEK_MT8195_PLL_H

#include <soc/pll_common.h>

/* top_div rate */
enum {
	CLK26M_HZ	= 26 * MHz,
};

/* top_mux rate */
enum {
	UART_HZ		= CLK26M_HZ,
};

#endif /* SOC_MEDIATEK_MT8195_PLL_H */