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| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-11-11 15:45:27 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-11-15 03:06:35 +0000 |
| commit | 7d9bd1757e778c59c5f9e96d673ce44c9a34d388 (patch) | |
| tree | c319e2c1dd563b39f60d11230c81e16a5d5c508c /src/soc/mediatek/mt8195/pll.c | |
| parent | 1e0765d85c3854a54783f01cd6e8194ccf6ca399 (diff) | |
| download | coreboot-7d9bd1757e778c59c5f9e96d673ce44c9a34d388.tar.gz coreboot-7d9bd1757e778c59c5f9e96d673ce44c9a34d388.tar.bz2 coreboot-7d9bd1757e778c59c5f9e96d673ce44c9a34d388.zip | |
soc/mediatek: move functions of mmu operation to common folder
Move mtk_soc_disable_l2c_sram and mtk_soc_after_dram to common folder
which are the same between MT8192, MT8195 and MT8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I8f49214b932a8d28ed2ca0d764dc745fa8ad330d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/pll.c')
| -rw-r--r-- | src/soc/mediatek/mt8195/pll.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 8fd424dc49ca..df4ae3039d6b 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -707,13 +707,13 @@ void mt_pll_init(void) } /* MCUCFG CLKMUX */ - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); /* enable infrasys DCM */ setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21); @@ -765,7 +765,7 @@ void mt_pll_init(void) void mt_pll_raise_little_cpu_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable armpll_ll frequency output */ clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN); @@ -778,13 +778,13 @@ void mt_pll_raise_little_cpu_freq(u32 freq) udelay(PLL_EN_DELAY); /* switch clock source back to armpll_ll */ - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } void mt_pll_raise_cci_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable ccipll frequency output */ clrbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN); @@ -797,7 +797,7 @@ void mt_pll_raise_cci_freq(u32 freq) udelay(PLL_EN_DELAY); /* switch clock source back to ccipll */ - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } void mt_pll_set_tvd_pll1_freq(u32 freq) |