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author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2021-05-04 10:32:54 +0800 |
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committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-05 07:37:05 +0000 |
commit | 1c920108499a7394bd072a7be380e491eac6fa28 (patch) | |
tree | c1f48b0ce4c6502fe6346069e146b0ae7b0b2747 /src/soc/mediatek/mt8195/spi.c | |
parent | f46e2caebec91d83bd729e6812e51ca960a24f38 (diff) | |
download | coreboot-1c920108499a7394bd072a7be380e491eac6fa28.tar.gz coreboot-1c920108499a7394bd072a7be380e491eac6fa28.tar.bz2 coreboot-1c920108499a7394bd072a7be380e491eac6fa28.zip |
soc/mediatek/mt8195: Add NOR-Flash support
TEST=boot to romstage on MT8195 EVB
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/spi.c')
-rw-r--r-- | src/soc/mediatek/mt8195/spi.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/spi.c b/src/soc/mediatek/mt8195/spi.c index bc02aa0e60e6..cfa52c436fab 100644 --- a/src/soc/mediatek/mt8195/spi.c +++ b/src/soc/mediatek/mt8195/spi.c @@ -3,6 +3,7 @@ #include <assert.h> #include <device/mmio.h> #include <soc/addressmap.h> +#include <soc/flash_controller_common.h> #include <soc/gpio.h> #include <soc/spi.h> @@ -93,6 +94,7 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, + .flash_probe = mtk_spi_flash_probe, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { @@ -103,6 +105,8 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { }, { .ctrlr = &spi_flash_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, }; |