soc/intel/xeon_sp: add MSR definitions for SPR-SP

Some MSRs used in SPR code are common among currently supported
Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs
which have changed are added to SPR's soc_msr.h.

Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>

2 files changed, 69 insertions, 2 deletions

diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h
index 377d33b402ea..19c37f6cb8b4 100644
--- a/src/soc/intel/xeon_sp/include/soc/msr.h
+++ b/src/soc/intel/xeon_sp/include/soc/msr.h
@@ -13,7 +13,7 @@
 #define IA32_MCG_CAP_CTL_P_BIT          8
 #define IA32_MCG_CAP_CTL_P_MASK         (1 << IA32_MCG_CAP_CTL_P_BIT)
 
-#define IA32_MCG_CTL                    0x17b
+#define IA32_MCG_CTL                    0x17b /* IA32_MCG_CAP[MCG_CTL_P] == 1 */
 
 /* IA32_MISC_ENABLE bits */
 #define FAST_STRINGS_ENABLE_BIT         (1 << 0)
@@ -27,7 +27,6 @@
 #define PKG_CSTATE_LIMIT_SHIFT           0 /* 0:3 */
 /* No package C-state limit. All C-States supported by the processor are available. */
 #define PKG_CSTATE_LIMIT_MASK            (0xf << PKG_CSTATE_LIMIT_SHIFT)
-#define PKG_CSTATE_NO_LIMIT              (0x7 << PKG_CSTATE_LIMIT_SHIFT)
 #define CFG_LOCK_SHIFT                   15
 #define CFG_LOCK_ENABLE                  (1 << CFG_LOCK_SHIFT)
 
@@ -35,6 +34,8 @@
 #define MSR_POWER_CTL                            0x1fc
 #define BIDIR_PROCHOT_ENABLE_SHIFT               0
 #define BIDIR_PROCHOT_ENABLE                     (1 << BIDIR_PROCHOT_ENABLE_SHIFT)
+#define C1E_ENABLE_SHIFT	     1
+#define C1E_ENABLE		     (1 << C1E_ENABLE_SHIFT)
 
 /* MSR_IA32_PERF_CTRL (0x199) bits */
 #define MSR_IA32_PERF_CTRL          0x199
@@ -64,11 +65,16 @@
 #define CURRENT_LIMIT_LOCK_SHIFT     31
 #define CURRENT_LIMIT_LOCK           (0x1 << CURRENT_LIMIT_LOCK_SHIFT)
 
+#define MSR_VR_MISC_CONFIG 0x603
+
 /* MSR_TURBO_ACTIVATION_RATIO bits */
 #define MSR_TURBO_ACTIVATION_RATIO   0x64c
 #define MAX_NON_TURBO_RATIO_SHIFT    0
 #define MAX_NON_TURBO_RATIO          (0xff << MAX_NON_TURBO_RATIO_SHIFT)
 
+#define IA32_PM_ENABLE 0x770
+#define IA32_HWP_CAPABILITIES 0x771
+
 /* MSR_ENERGY_PERF_BIAS_CONFIG bits */
 #define MSR_ENERGY_PERF_BIAS_CONFIG  0xa01
 #define EPB_ENERGY_POLICY_SHIFT      3
diff --git a/src/soc/intel/xeon_sp/spr/include/soc/soc_msr.h b/src/soc/intel/xeon_sp/spr/include/soc/soc_msr.h
new file mode 100644
index 000000000000..cfae169222c1
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/include/soc/soc_msr.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_MSR_SPR_H_
+#define _SOC_MSR_SPR_H_
+
+#define MSR_CPU_BUSNO 0x128
+#define BUSNO_VALID   (1 << 31)	/* used as msr.hi */
+
+/* IA32_ERR_CTRL */
+#define CMCI_DISABLE (1 << 4)
+
+/* MSR_PKG_CST_CONFIG_CONTROL */
+#define PKG_CSTATE_NO_LIMIT (0x8 << PKG_CSTATE_LIMIT_SHIFT)
+
+/* MSR_POWER_CTL */
+#define RESERVED1_SHIFT		     2
+#define PWR_PERF_PLTFRM_OVR_SHIFT    18
+#define PWR_PERF_PLTFRM_OVR	     (1 << PWR_PERF_PLTFRM_OVR_SHIFT)
+#define EE_TURBO_DISABLE_SHIFT	     19
+#define EE_TURBO_DISABLE	     (1 << EE_TURBO_DISABLE_SHIFT)
+#define RTH_DISABLE_SHIFT	     20
+#define RTH_DISABLE		     (1 << RTH_DISABLE_SHIFT)
+#define PROCHOT_OUTPUT_DISABLE_SHIFT 21
+#define PROCHOT_OUTPUT_DISABLE	     (1 << PROCHOT_OUTPUT_DISABLE_SHIFT)
+#define PROCHOT_RESPONSE_SHIFT	     22
+#define PROCHOT_RESPONSE	     (1 << PROCHOT_RESPONSE_SHIFT)
+#define PROCHOT_LOCK_SHIFT	     23
+#define PROCHOT_LOCK		     (1 << PROCHOT_LOCK_SHIFT)
+#define VR_THERM_ALERT_DISABLE_SHIFT 24
+#define VR_THERM_ALERT_DISABLE	     (1 << VR_THERM_ALERT_DISABLE_SHIFT)
+#define DISABLE_RING_EE_SHIFT	     25
+#define DISABLE_RING_EE		     (1 << DISABLE_RING_EE_SHIFT)
+#define RESERVED2_SHIFT		     26
+#define DISABLE_AUTONOMOUS_SHIFT     28
+#define DISABLE_AUTONOMOUS	     (1 << DISABLE_AUTONOMOUS_SHIFT)
+#define RESERVED3_SHIFT		     29
+#define CSTATE_PREWAKE_DISABLE_SHIFT 30
+#define CSTATE_PREWAKE_DISABLE	     (1 << CSTATE_PREWAKE_DISABLE_SHIFT)
+
+/* SPR has banks 0-20 and 29-31 */
+#define IA32_MC20_CTL2	   0x294
+#define IA32_MC29_CTL2	   0x29D
+#define IA32_MC30_CTL2	   0x29E
+#define IA32_MC31_CTL2	   0x29F
+
+#define MSR_PERRINJ_AT_IP	 0x107
+#define MSR_PERRINJ_AT_IP_ENABLE BIT(31)
+
+#define MSR_BIOS_DONE		    0x151
+#define XEON_SP_ENABLE_IA_UNTRUSTED BIT(0)
+
+#define MSR_FLEX_RATIO	       0x194
+#define MSR_FLEX_RATIO_OC_LOCK BIT(20)
+
+/* B1:D30:F0 offset 0xe8 on previous generations */
+#define PACKAGE_RAPL_LIMIT 0x610
+
+#define MSR_DRAM_PLANE_POWER_LIMIT 0x618
+#define MSR_HI_PP_PWR_LIM_LOCK	   BIT(31)	/* used as msr.hi */
+
+#endif /* _SOC_MSR_SPR_H_ */