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author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/southbridge/amd/rs780/rs780.c | |
parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
download | coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.gz coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.bz2 coreboot-b0f1988f893bf5f581917816b11e810309955143.zip |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/rs780/rs780.c')
-rw-r--r-- | src/southbridge/amd/rs780/rs780.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index ef40ffd0606a..f4f33efab78b 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -93,7 +93,7 @@ void static rs780_config_misc_clk(struct device *nb_dev) byte |= 1 << 0; pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg); - /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ + /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ /* TODO: */ #endif |