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| author | Elyes Haouas <ehaouas@noos.fr> | 2022-10-27 12:25:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-03 13:05:17 +0000 |
| commit | 35c3ae3bf4a43a36028fbd9e34ea4cb758029bf1 (patch) | |
| tree | 4b706d4931692f6cde4d16339d7de1b0bf5f1e55 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 109bd3b796bae2f8333d832e9f0cc778c6663297 (diff) | |
| download | coreboot-35c3ae3bf4a43a36028fbd9e34ea4cb758029bf1.tar.gz coreboot-35c3ae3bf4a43a36028fbd9e34ea4cb758029bf1.tar.bz2 coreboot-35c3ae3bf4a43a36028fbd9e34ea4cb758029bf1.zip | |
treewide: Add 'IWYU pragma: export' comment
This pragma says to IWYU (Include What You Use) that the current file
is supposed to provide commented headers.
Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 15d908ac95a8..34b36c38661a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -22,7 +22,7 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) #define CROS_GPIO_DEVICE_NAME "CougarPoint" |