lynxpoint: Fix an issue clearing port change status bits

The coreboot and ACPI code that clears USB3 PORTSC change status
bits was not properly preserving the state of the PED (port enabled
or disabled) status bit, and it could write 0 back to this field
which would disable the port.

Additionally add back the code that resets disconnected USB3 ports
on the way into suspend (as stated in the BWG) but take care to
clear the PME status bit so we don't immediately wake.

suspend/resume with USB3 devices

1) suspend with no devices, plug in while suspended, then resume
and verify that the devices are detected
2) suspend with USB3 devices inserted, then suspend and resume
and verify that the devices are detected
3) suspend with USB3 devices inserted, then remove the devices
while suspended, resume and ensure they can be detected again
when inserted after resume

Change-Id: Ic7e8d375dfe645cf0dc1f041c3a3d09d0ead1a51
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65733
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4473
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 25 insertions, 12 deletions

diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl
index c22dbb80bc9a..2fe67506b852 100644
--- a/src/southbridge/intel/lynxpoint/acpi/usb.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl
@@ -106,23 +106,36 @@ Device (XHCI)
 		Field (XREG, DWordAcc, Lock, Preserve)
 		{
 			Offset (0x510), // PORTSCNUSB3[0]
-			, 17,
-			CLR1, 7,	// Status Change bits 23:17
+			PSC0, 32,
 			Offset (0x520), // PORTSCNUSB3[1]
-			, 17,
-			CLR2, 7,	// Status Change Bits 23:17
+			PSC1, 32,
 			Offset (0x530), // PORTSCNUSB3[2]
-			, 17,
-			CLR3, 7,	// Status Change Bits 23:17
+			PSC2, 32,
 			Offset (0x540), // PORTSCNUSB3[3]
-			, 17,
-			CLR4, 7,	// Status Change Bits 23:17
+			PSC3, 32,
 		}
 
-		Store (0x7f, CLR1)
-		Store (0x7f, CLR2)
-		Store (0x7f, CLR3)
-		Store (0x7f, CLR4)
+		// Port Enabled/Disabled (Bit 1)
+		Name (PEDB, ShiftLeft (1, 1))
+
+		// Change Status (Bits 23:17)
+		Name (CHST, ShiftLeft (0x7f, 17))
+
+		// Port 0
+		And (PSC0, Not (PEDB), Local0)
+		Or (Local0, CHST, PSC0)
+
+		// Port 1
+		And (PSC1, Not (PEDB), Local0)
+		Or (Local0, CHST, PSC1)
+
+		// Port 2
+		And (PSC2, Not (PEDB), Local0)
+		Or (Local0, CHST, PSC2)
+
+		// Port 3
+		And (PSC3, Not (PEDB), Local0)
+		Or (Local0, CHST, PSC3)
 	}
 
 	Method (LPS0, 0, Serialized)