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path: root/src/southbridge/intel/lynxpoint/acpi/usb.asl
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* sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCIAngel Pons2020-11-131-377/+0
* sb/intel/lynxpoint/acpi: Statically define _PRW valuesAngel Pons2020-11-131-20/+2
* sb/intel/lynxpoint/acpi: Clean up cosmeticsAngel Pons2020-11-131-98/+84
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src/southbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-041-14/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-1/+0
* sb/lynxpoint: add missing USB port defsMatt DeVillier2017-05-311-2/+5
* sb/lynxpoint: add ACPI method to generate USB port infoMatt DeVillier2017-05-311-0/+16
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-2/+1
* southbridge,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-171-1/+0
* lynxpoint: XHCI: Don't put device in D3 in _PS0 MethodDuncan Laurie2013-12-211-8/+1
* lynxpoint: Fix an issue clearing port change status bitsDuncan Laurie2013-12-211-12/+25
* lynxpoint: XHCI: Advertise D3 as lowest wake stateDuncan Laurie2013-12-211-2/+7
* lynxpoint xhci: Add ACPI D0/D3 workaroundsDuncan Laurie2013-12-211-1/+291
* lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objectsDuncan Laurie2013-12-031-2/+20
* lynxpoint: Fix XHCI controller device in ACPIDuncan Laurie2013-11-251-6/+6
* haswell: Add initial support for Haswell platformsAaron Durbin2013-03-141-0/+91
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