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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-10 17:53:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-21 09:27:31 +0000 |
| commit | 84d10cc5d38d706ffecd0cd60f6e1f9d90064f96 (patch) | |
| tree | f5497cb6cb0c236cbb0b1ab002e75d8e73e5efe4 /src/vendorcode/google | |
| parent | 307be997d1acd604a573e2ab895ef10570454fc4 (diff) | |
| download | coreboot-84d10cc5d38d706ffecd0cd60f6e1f9d90064f96.tar.gz coreboot-84d10cc5d38d706ffecd0cd60f6e1f9d90064f96.tar.bz2 coreboot-84d10cc5d38d706ffecd0cd60f6e1f9d90064f96.zip | |
ChromeOS: Use CHROMEOS_NVS guard
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where
the conditional and dependency are clearly about the presence of
an ACPI NVS table specified by vendorcode. For couple locations also
CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS).
This also helps find some of the CONFIG(CHROMEOS) cases that might
be more FMAP and VPD related and not about ChromeOS per-se, as
suggested by followup works.
Change-Id: Ife888ae43093949bb2d3e397565033037396f434
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/google')
| -rw-r--r-- | src/vendorcode/google/chromeos/Kconfig | 5 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/ramoops.c | 2 |
3 files changed, 7 insertions, 2 deletions
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index e81f31d19663..e6d45e14cea4 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -12,6 +12,7 @@ config CHROMEOS select ELOG if BOOT_DEVICE_SUPPORTS_WRITES select COLLECT_TIMESTAMPS select VBOOT + select CHROMEOS_NVS if ACPI_SOC_NVS select VPD select VBOOT_SLOTS_RW_AB help @@ -87,5 +88,9 @@ config CHROMEOS_DRAM_PART_NUMBER_IN_CBI Some boards declare the DRAM part number in the CBI instead of the SPD. This option allows those boards to declare that their DRAM part number is stored in the CBI. +config CHROMEOS_NVS + bool + depends on ACPI_SOC_NVS + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index ba00d7778c60..c05d8e727ab3 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_ELOG) += elog.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c +ramstage-$(CONFIG_CHROMEOS_NVS) += gnvs.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 77e079f2b140..3b658b70e51e 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -38,7 +38,7 @@ static void ramoops_alloc(void *arg) return; } - if (CONFIG(HAVE_ACPI_TABLES)) + if (CONFIG(CHROMEOS_NVS)) set_ramoops(ram_oops, size); } |