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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-01-22 23:48:52 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-25 10:44:03 +0000 |
| commit | 06e067e4cf7a7b455a4574c3c62391de23973bb7 (patch) | |
| tree | 0399f0c3722a5ffad0e1d86543941ebde2dfe257 /src | |
| parent | 591b0ff535d36f0f69e92c55fe465cbf70dcbfe4 (diff) | |
| download | coreboot-06e067e4cf7a7b455a4574c3c62391de23973bb7.tar.gz coreboot-06e067e4cf7a7b455a4574c3c62391de23973bb7.tar.bz2 coreboot-06e067e4cf7a7b455a4574c3c62391de23973bb7.zip | |
mb/intel/tglrvp: Enable rp11 for optane
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage
device and NVMe Optane memory. Storage device uses rp9 and optane memory
uses rp11. This patch enables rp11. Please note that these two share clk pins.
This is also dependent on pciecontroller3 config to be set as 2x2 instead of
1x4 in fit configuration in IFWI.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices
from lspci
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 01e0f3f8f8f3..e7bfe337f955 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -35,7 +35,7 @@ chip soc/intel/tigerlake register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" @@ -139,8 +139,8 @@ chip soc/intel/tigerlake device pci 1c.6 off end # RP7 0xA0BE device pci 1c.7 off end # RP8 0xA0BF device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 on end # RP10 0xA0B1 - device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.1 off end # RP10 0xA0B1 + device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3 device pci 1e.0 off end # UART0 0xA0A8 device pci 1e.1 off end # UART1 0xA0A9 |