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| author | Bill XIE <persmule@hardenedlinux.org> | 2022-07-07 16:18:57 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-07-30 18:39:31 +0000 |
| commit | 4e43abf9c120b5a9ae4d920a71df1c7993e6a617 (patch) | |
| tree | 338f77db7b370fd10f57103e467f19892c5d7802 /src | |
| parent | a955efc190475bc1746c872395729a285c95d95e (diff) | |
| download | coreboot-4e43abf9c120b5a9ae4d920a71df1c7993e6a617.tar.gz coreboot-4e43abf9c120b5a9ae4d920a71df1c7993e6a617.tar.bz2 coreboot-4e43abf9c120b5a9ae4d920a71df1c7993e6a617.zip | |
mb/hp/z220_series: Improve the port for z220_sff_workstation
- Move configs for PCIe ports not present on z220_sff_workstation
from the devicetree.cb of base board to the overridetree.cb of
z220_cmt_workstation.
- Add a note for ME/AMT Flash Override jumper, for it is hard to
flash from OEM firmware either internally or externally without
closing this jumper.
- Add a side note for similar HP Compaq Elite 8300 SFF.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/hp/z220_series/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index 4611bec14089..ea8fad93205a 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -22,6 +22,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on end # Host bridge Host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on end # Internal graphics VGA controller + device pci 06.0 off end # Extra x4 port on north bridge chip southbridge/intel/bd82x6x # Intel Series 7 PCH register "docking_supported" = "0" @@ -47,8 +48,8 @@ chip northbridge/intel/sandybridge device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 on end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge diff --git a/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb index 2e46d2a0b691..55bdaac23a2a 100644 --- a/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb +++ b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x103c 0x1791 inherit + device pci 06.0 on end # Extra x4 port on north bridge chip southbridge/intel/bd82x6x register "sata_port_map" = "0x3f" @@ -10,6 +11,8 @@ chip northbridge/intel/sandybridge device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 on end # PCIe Port #4 device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 end end end |