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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2022-07-28 16:57:26 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-01 12:36:31 +0000 |
| commit | 6e3d40f2d1f78ddb599073dbcb22c887228ba4c3 (patch) | |
| tree | 9b847eb95e74d140caa06544843d78cf81ee6f93 /src | |
| parent | 63696fcf90159179b8ecec264e8867ea884dd87d (diff) | |
| download | coreboot-6e3d40f2d1f78ddb599073dbcb22c887228ba4c3.tar.gz coreboot-6e3d40f2d1f78ddb599073dbcb22c887228ba4c3.tar.bz2 coreboot-6e3d40f2d1f78ddb599073dbcb22c887228ba4c3.zip | |
Revert "UPSTREAM: soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for Sabrina"
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.
Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.
BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/sabrina/psp_verstage/uart.c | 19 | ||||
| -rw-r--r-- | src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h | 7 |
2 files changed, 2 insertions, 24 deletions
diff --git a/src/soc/amd/sabrina/psp_verstage/uart.c b/src/soc/amd/sabrina/psp_verstage/uart.c index 2767b2eb27d9..1c89f10c9928 100644 --- a/src/soc/amd/sabrina/psp_verstage/uart.c +++ b/src/soc/amd/sabrina/psp_verstage/uart.c @@ -4,23 +4,8 @@ #include <amdblocks/uart.h> #include <types.h> -static void *uart_bars[FCH_UART_ID_MAX]; - uintptr_t get_uart_base(unsigned int idx) { - uint32_t err; - - if (idx >= ARRAY_SIZE(uart_bars)) - return 0; - - if (uart_bars[idx]) - return (uintptr_t)uart_bars[idx]; - - err = svc_map_fch_dev(FCH_IO_DEVICE_UART, idx, 0, &uart_bars[idx]); - if (err) { - svc_debug_print("Failed to map UART\n"); - return 0; - } - - return (uintptr_t)uart_bars[idx]; + /* Mapping the UART is not supported. */ + return 0; } diff --git a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h index 79e3adfb9156..48c35e54ac83 100644 --- a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h @@ -91,16 +91,9 @@ enum fch_io_device { FCH_IO_DEVICE_MISC, FCH_IO_DEVICE_AOAC, FCH_IO_DEVICE_IOPORT, - FCH_IO_DEVICE_UART, FCH_IO_DEVICE_END, }; -enum fch_uart_id { - FCH_UART_ID_0 = 0, - FCH_UART_ID_1 = 1, - FCH_UART_ID_MAX, -}; - enum fch_i2c_controller_id { FCH_I2C_CONTROLLER_ID_0 = 0, FCH_I2C_CONTROLLER_ID_1 = 1, |