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| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-19 16:02:45 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-05 10:55:58 +0000 |
| commit | 81e9263caabb7735f01f61d046c3c4df91badcab (patch) | |
| tree | c96e0efe8507cc62c9b6b1e16cac27bcb7423fb9 /src | |
| parent | e4606bbff79ef1b0771417a1ee4e3bb0fb1909c2 (diff) | |
| download | coreboot-81e9263caabb7735f01f61d046c3c4df91badcab.tar.gz coreboot-81e9263caabb7735f01f61d046c3c4df91badcab.tar.bz2 coreboot-81e9263caabb7735f01f61d046c3c4df91badcab.zip | |
soc/intel/apollolake: Add `GPE0_STS_BIT` macro
The datasheet indicates that this bit is reserved. However, subsequent
patches need to use this macro in common code, or else builds fail. To
iron out this difference, mask out the bit in `soc_get_smi_status`, so
that common code always sees it as zero. Finally, add an entry for the
bit in `smi_sts_bits` for debugging usage, noting that it is reserved.
Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/pmutil.c | 7 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index b40a12fce33e..bc50b87d4501 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -108,6 +108,7 @@ #define MC_SMI_STS_BIT 12 #define GPIO_UNLOCK_SMI_STS_BIT 11 #define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 /* Datasheet says this is reserved */ #define PM1_STS_BIT 8 #define SWSMI_TMR_STS_BIT 6 #define APM_STS_BIT 5 diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 1d4a55835eed..8f222dd244c7 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -48,6 +48,7 @@ const char *const *soc_smi_sts_array(size_t *a) [APM_STS_BIT] = "APM", [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", [PM1_STS_BIT] = "PM1", + [GPE0_STS_BIT] = "GPE0 (reserved)", [GPIO_STS_BIT] = "GPIO_SMI", [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI", [MC_SMI_STS_BIT] = "MCSMI", @@ -86,7 +87,11 @@ uint32_t soc_get_smi_status(uint32_t generic_sts) generic_sts |= (1 << PM1_STS_BIT); } - return generic_sts; + /* + * GPE0_STS is reserved in APL/GLK datasheets. For compatibility + * with common code, mask it out so that it is always zero. + */ + return generic_sts & ~(1 << GPE0_STS_BIT); } const char *const *soc_tco_sts_array(size_t *a) |