diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-01 18:11:13 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-03 09:07:04 +0000 |
| commit | b0f52fb5bfa71d2ddf5741408cc14fcfdf8f5ffc (patch) | |
| tree | b863f6313300b552af523beb47538f777773c430 /src | |
| parent | a4cd9117daee91ab4ffb8ab6e8d7d62142920585 (diff) | |
| download | coreboot-b0f52fb5bfa71d2ddf5741408cc14fcfdf8f5ffc.tar.gz coreboot-b0f52fb5bfa71d2ddf5741408cc14fcfdf8f5ffc.tar.bz2 coreboot-b0f52fb5bfa71d2ddf5741408cc14fcfdf8f5ffc.zip | |
soc/intel/cannonlake: Move `gpi_clear_int_cfg()` call
To allow unifying bootblock.c in follow-ups, move a function call.
Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/bootblock.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 7 |
2 files changed, 7 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index dfa0bd00b5f4..1354c43a22e4 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -61,11 +61,6 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { - /* - * Clear the GPI interrupt status and enable registers. These - * registers do not get reset to default state when booting from S5. - */ - gpi_clear_int_cfg(); report_platform_info(); bootblock_pch_init(); diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 51f8fb59f673..a4f47c990b4e 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -6,6 +6,7 @@ #include <device/pci_ops.h> #include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gpio.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> @@ -132,6 +133,12 @@ void pch_early_iorange_init(void) void bootblock_pch_init(void) { /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); + + /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, * GPE0_STS, GPE0_EN registers. */ |