diff options
33 files changed, 62 insertions, 73 deletions
diff --git a/device/device.c b/device/device.c index ca0d96e1d8a6..728d3d6d26a8 100644 --- a/device/device.c +++ b/device/device.c @@ -754,14 +754,14 @@ void dev_phase2(void) printk(BIOS_DEBUG, "Phase 2: Early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { printk(BIOS_SPEW, - "%s: dev %s: ops %p ops->phase2_setup_scan_bus %p\n", + "%s: dev %s: ops %p ops->phase2_fixup %p\n", __FUNCTION__, dev->dtsname, dev->ops, - dev->ops? dev->ops->phase2_setup_scan_bus : NULL); - if (dev->ops && dev->ops->phase2_setup_scan_bus) { + dev->ops? dev->ops->phase2_fixup : NULL); + if (dev->ops && dev->ops->phase2_fixup) { printk(BIOS_SPEW, - "Calling phase2 phase2_setup_scan_bus...\n"); - dev->ops->phase2_setup_scan_bus(dev); - printk(BIOS_SPEW, "phase2_setup_scan_bus done\n"); + "Calling phase2 phase2_fixup...\n"); + dev->ops->phase2_fixup(dev); + printk(BIOS_SPEW, "phase2_fixup done\n"); } } @@ -797,14 +797,12 @@ unsigned int dev_phase3_scan(struct device *busdevice, unsigned int max) return max; } - if (busdevice->ops->phase3_enable_scan) - busdevice->ops->phase3_enable_scan(busdevice); - do_phase3 = 1; while (do_phase3) { int link; printk(BIOS_INFO, "%s: scanning %s(%s)\n", __FUNCTION__, busdevice->dtsname, dev_path(busdevice)); +#warning do we call phase3_enable here. new_max = busdevice->ops->phase3_scan(busdevice, max); do_phase3 = 0; for (link = 0; link < busdevice->links; link++) { @@ -853,8 +851,8 @@ void dev_root_phase3(void) printk(BIOS_INFO, "Phase 3: Enumerating buses...\n"); root = &dev_root; - if (root->ops && root->ops->phase3_enable_scan) { - root->ops->phase3_enable_scan(root); + if (root->ops && root->ops->phase3_chip_setup_dev) { + root->ops->phase3_chip_setup_dev(root); } post_code(POST_STAGE2_PHASE3_MIDDLE); if (!root->ops) { diff --git a/device/pci_device.c b/device/pci_device.c index 37a7a9aeaae3..b709953c4847 100644 --- a/device/pci_device.c +++ b/device/pci_device.c @@ -739,7 +739,6 @@ struct device_operations default_pci_ops_dev = { .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = pci_dev_init, .phase3_scan = 0, - .phase4_enable_disable = 0, .ops_pci = &pci_dev_ops_pci, }; @@ -749,12 +748,11 @@ struct pci_operations pci_bus_ops_pci = { }; struct device_operations default_pci_ops_bus = { + .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = 0, - .phase3_scan = pci_scan_bridge, - .phase4_enable_disable = 0, .reset_bus = pci_bus_reset, .ops_pci = &pci_bus_ops_pci, }; @@ -1006,8 +1004,8 @@ struct device *pci_probe_dev(struct device *dev, struct bus *bus, * it may be absent and enable_dev() must cope. */ /* Run the magic enable sequence for the device. */ - if (dev->ops && dev->ops->phase3_enable_scan) { - dev->ops->phase3_enable_scan(dev); + if (dev->ops && dev->ops->phase3_chip_setup_dev) { + dev->ops->phase3_chip_setup_dev(dev); } /* Now read the vendor and device ID. */ id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -1062,8 +1060,8 @@ struct device *pci_probe_dev(struct device *dev, struct bus *bus, set_pci_ops(dev); /* Now run the magic enable/disable sequence for the device. */ - if (dev->ops && dev->ops->phase4_enable_disable) { - dev->ops->phase4_enable_disable(dev); + if (dev->ops && dev->ops->phase3_enable) { + dev->ops->phase3_enable(dev); } /* Display the device and error if we don't have some PCI operations diff --git a/device/pci_rom.c b/device/pci_rom.c index f8e91a759089..443f52b62df6 100644 --- a/device/pci_rom.c +++ b/device/pci_rom.c @@ -108,7 +108,8 @@ struct rom_header *pci_rom_probe(struct device *dev) rom_data = (struct pci_data *)((unsigned char *)rom_header + le32_to_cpu(rom_header->data)); - printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n", + printk(BIOS_SPEW, "PCI ROM Image, @%p, Vendor %04x, Device %04x,\n", + &rom_data->vendor, rom_data->vendor, rom_data->device); if (dev->id.pci.vendor != rom_data->vendor || dev->id.pci.device != rom_data->device) { printk(BIOS_ERR, diff --git a/device/root_device.c b/device/root_device.c index 98967323cede..433493c57fc1 100644 --- a/device/root_device.c +++ b/device/root_device.c @@ -119,12 +119,12 @@ unsigned int scan_static_bus(struct device *busdevice, unsigned int max) } for (child = busdevice->link[link].children; child; child = child->sibling) { - if (child->ops && child->ops->phase3_enable_scan) { - child->ops->phase3_enable_scan(child); + if (child->ops && child->ops->phase3_chip_setup_dev) { + child->ops->phase3_chip_setup_dev(child); } /* Sigh. Have to enable to scan... */ - if (child->ops && child->ops->phase5_enable_resources) { - child->ops->phase5_enable_resources(child); + if (child->ops && child->ops->phase3_enable) { + child->ops->phase3_enable(child); } if (child->path.type == DEVICE_PATH_I2C) { printk(BIOS_DEBUG, "smbus: %s(%s)[%d]->", @@ -217,11 +217,11 @@ void root_dev_reset(struct bus *bus) * mainboard directory. */ struct device_operations default_dev_ops_root = { + .phase3_scan = root_dev_scan_bus, .phase4_read_resources = root_dev_read_resources, .phase4_set_resources = root_dev_set_resources, .phase5_enable_resources = root_dev_enable_resources, .phase6_init = root_dev_init, - .phase3_scan = root_dev_scan_bus, .reset_bus = root_dev_reset, }; diff --git a/include/device/device.h b/include/device/device.h index cbd861640c0f..392f4ba27475 100644 --- a/include/device/device.h +++ b/include/device/device.h @@ -143,19 +143,19 @@ struct device_operations { void (*phase1_set_device_operations)(struct device *dev); /* phase 2 is for any magic you have to do before the busses are scanned */ - void (*phase2_setup_scan_bus)(struct device * dev); + void (*phase2_fixup)(struct device * dev); /* phase 3 is for scanning the bus, if needed. */ - void (*phase3_enable_scan)(struct device *dev); + void (*phase3_chip_setup_dev)(struct device *dev); + /* some devices need to be enabled to scan. */ + /* this function enables/disables according the value of 'enabled' in the device*/ + void (*phase3_enable)(struct device * dev); unsigned int (*phase3_scan)(struct device * bus, unsigned int max); /* typically used by phase4 */ /* again, if we never use this anywhere else, we may change the names */ void (*phase4_read_resources)(struct device * dev); void (*phase4_set_resources)(struct device * dev); - /* some devices need to be enabled to scan, then disabled again. */ - /* this function enables/disables according the value of 'enabled' in the device*/ - void (*phase4_enable_disable)(struct device * dev); /* phase 5: enable devices */ void (*phase5_enable_resources)(struct device * dev); diff --git a/mainboard/amd/dbm690t/mainboard.c b/mainboard/amd/dbm690t/mainboard.c index 5b470df6fc0d..ecda109deb51 100644 --- a/mainboard/amd/dbm690t/mainboard.c +++ b/mainboard/amd/dbm690t/mainboard.c @@ -129,5 +129,5 @@ struct device_operations dbm690t = { {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = 1}}}, .constructor = default_device_constructor, - .phase3_enable_scan = dbm690t_enable, + .phase3_chip_setup_dev = dbm690t_enable, }; diff --git a/mainboard/amd/serengeti/dts b/mainboard/amd/serengeti/dts index bed930b76277..a50b49c0f905 100644 --- a/mainboard/amd/serengeti/dts +++ b/mainboard/amd/serengeti/dts @@ -46,7 +46,6 @@ /config/("southbridge/amd/amd8111/usb2.dts"); }; pci@4,0{ - rom_address = "0xfc000000"; }; }; pci@7,0 { diff --git a/mainboard/emulation/qemu-x86/vga.c b/mainboard/emulation/qemu-x86/vga.c index e1684ce93c27..d233a1e0b8fb 100644 --- a/mainboard/emulation/qemu-x86/vga.c +++ b/mainboard/emulation/qemu-x86/vga.c @@ -40,6 +40,8 @@ static void setup_onboard(struct device *dev) * but since QEMU has no Super I/O... */ init_pc_keyboard(0x60, 0x64, &conf); + /* now run the rom */ + pci_dev_init(dev); } struct device_operations qemuvga_pci_ops_dev = { @@ -50,9 +52,8 @@ struct device_operations qemuvga_pci_ops_dev = { .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = setup_onboard, .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = pci_dev_init, + .phase6_init = setup_onboard, .ops_pci = &pci_dev_ops_pci, }; diff --git a/northbridge/amd/geodelx/geodelx.c b/northbridge/amd/geodelx/geodelx.c index 961d829db076..79616b839c10 100644 --- a/northbridge/amd/geodelx/geodelx.c +++ b/northbridge/amd/geodelx/geodelx.c @@ -227,7 +227,7 @@ struct device_operations geodelx_north_domain = { {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, - .phase2_setup_scan_bus = geodelx_pci_domain_phase2, + .phase2_fixup = geodelx_pci_domain_phase2, .phase3_scan = pci_domain_scan_bus, .phase4_read_resources = pci_domain_read_resources, .phase4_set_resources = geodelx_pci_domain_set_resources, diff --git a/southbridge/amd/amd8111/ac97.c b/southbridge/amd/amd8111/ac97.c index fdf6ab322e40..4893dfedac30 100644 --- a/southbridge/amd/amd8111/ac97.c +++ b/southbridge/amd/amd8111/ac97.c @@ -44,7 +44,7 @@ struct device_operations ac97audio = { .device = 0x746D}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -58,7 +58,7 @@ struct device_operations ac97modem = { .device = 0x746E}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/amd8111/acpi.c b/southbridge/amd/amd8111/acpi.c index 28867185ee8f..9b8a7622a4ae 100644 --- a/southbridge/amd/amd8111/acpi.c +++ b/southbridge/amd/amd8111/acpi.c @@ -231,7 +231,7 @@ struct device_operations acpi = { .device = PCI_DEVICE_ID_AMD_8111_ACPI}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = acpi_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = acpi_enable_resources, diff --git a/southbridge/amd/amd8111/ide.c b/southbridge/amd/amd8111/ide.c index b34c4f5e1552..c56339e7a3ac 100644 --- a/southbridge/amd/amd8111/ide.c +++ b/southbridge/amd/amd8111/ide.c @@ -78,7 +78,7 @@ struct device_operations amd8111_ide = { .device = PCI_DEVICE_ID_AMD_8111_IDE}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/amd8111/lpc.c b/southbridge/amd/amd8111/lpc.c index 67dcb1002d42..d66c4e54460b 100644 --- a/southbridge/amd/amd8111/lpc.c +++ b/southbridge/amd/amd8111/lpc.c @@ -213,7 +213,7 @@ struct device_operations amd8111_lpc = { .device = PCI_DEVICE_ID_AMD_8111_ISA}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = amd8111_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = amd8111_lpc_enable_resources, diff --git a/southbridge/amd/amd8111/nic.c b/southbridge/amd/amd8111/nic.c index 004f9fde2609..baaf05a30161 100644 --- a/southbridge/amd/amd8111/nic.c +++ b/southbridge/amd/amd8111/nic.c @@ -99,7 +99,7 @@ struct device_operations amd8111_nic = { .device = PCI_DEVICE_ID_AMD_8111_NIC}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/amd8111/pci.c b/southbridge/amd/amd8111/pci.c index 5dfb46380b10..26b17a7f2775 100644 --- a/southbridge/amd/amd8111/pci.c +++ b/southbridge/amd/amd8111/pci.c @@ -75,7 +75,7 @@ struct device_operations amd8111_pci = { .device = PCI_DEVICE_ID_AMD_8111_PCI}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, diff --git a/southbridge/amd/amd8111/smbus.c b/southbridge/amd/amd8111/smbus.c index 1b9b26fcc55a..599d174973c7 100644 --- a/southbridge/amd/amd8111/smbus.c +++ b/southbridge/amd/amd8111/smbus.c @@ -53,7 +53,7 @@ struct device_operations amd8111_smbus = { .device = PCI_DEVICE_ID_AMD_8111_SMB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/amd8111/usb.c b/southbridge/amd/amd8111/usb.c index 8f501be07691..36028857a035 100644 --- a/southbridge/amd/amd8111/usb.c +++ b/southbridge/amd/amd8111/usb.c @@ -50,7 +50,7 @@ struct device_operations amd8111_usb = { .device = PCI_DEVICE_ID_AMD_8111_USB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/amd8111/usb2.c b/southbridge/amd/amd8111/usb2.c index 24f9d365ee12..81f135eec481 100644 --- a/southbridge/amd/amd8111/usb2.c +++ b/southbridge/amd/amd8111/usb2.c @@ -49,7 +49,7 @@ struct device_operations amd8111_usb2 = { .device = PCI_DEVICE_ID_AMD_8111_USB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_usb2_enable, + .phase3_chip_setup_dev = amd8111_usb2_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/rs690/gfx.c b/southbridge/amd/rs690/gfx.c index cf89da1000c4..90e8d1a637bf 100644 --- a/southbridge/amd/rs690/gfx.c +++ b/southbridge/amd/rs690/gfx.c @@ -79,13 +79,9 @@ static void internal_gfx_pci_dev_init(struct device *dev) struct southbridge_amd_rs690_gfx_config *cfg = dev->device_configuration; deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%x.\n", + printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%lx.\n", deviceid, vendorid, cfg->vga_rom_address); -#if 0 /* I think these should be done in Config.lb. Please check it. */ - dev->on_mainboard = 1; - dev->rom_address = cfg->vga_rom_address; /* 0xfff00000; */ -#endif pci_dev_init(dev); /* clk ind */ @@ -569,9 +565,9 @@ struct device_operations rs690_gfx = { {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX}}}, .constructor = default_device_constructor, - .phase2_setup_scan_bus = rs690_internal_gfx_enable, + .phase3_chip_setup_dev = rs690_enable, + .phase3_enable = rs690_internal_gfx_enable, .phase3_scan = 0, - .phase4_enable_disable = rs690_enable, .phase4_read_resources = rs690_gfx_read_resources, .phase4_set_resources = rs690_gfx_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/rs690/gfx.dts b/southbridge/amd/rs690/gfx.dts index 43c1290c1934..4b326f88a44c 100644 --- a/southbridge/amd/rs690/gfx.dts +++ b/southbridge/amd/rs690/gfx.dts @@ -33,7 +33,7 @@ */ { device_operations = "rs690_gfx"; - vga_rom_address = "0xfff00000"; /* The location that the VGA rom has been appened. */ + vga_rom_address = "0xfff0000"; gfx_dev2_dev3 = "1"; /* for GFX Core initialization REFCLK_SEL */ gfx_dual_slot = "0"; /* Is it dual graphics slots */ gfx_lane_reversal = "0"; /* Single/Dual slot lan reversal */ diff --git a/southbridge/amd/rs690/ht.c b/southbridge/amd/rs690/ht.c index 4d6f6ff36f46..28d6bcb4102e 100644 --- a/southbridge/amd/rs690/ht.c +++ b/southbridge/amd/rs690/ht.c @@ -85,9 +85,8 @@ struct device_operations rs690_ht = { {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS690_HT}}}, .constructor = default_device_constructor, - .phase2_setup_scan_bus = rs690_enable, .phase3_scan = 0, - .phase4_enable_disable = rs690_enable, + .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/rs690/pcie.c b/southbridge/amd/rs690/pcie.c index ab6444800387..bc954cd51a9c 100644 --- a/southbridge/amd/rs690/pcie.c +++ b/southbridge/amd/rs690/pcie.c @@ -400,7 +400,7 @@ struct device_operations rs690_pcie = { .device = PCI_DEVICE_ID_ATI_RS690_PCIE}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase4_enable_disable = rs690_enable, + .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, diff --git a/southbridge/amd/sb600/ac97.c b/southbridge/amd/sb600/ac97.c index 5322a89ab544..0ecdbf613886 100644 --- a/southbridge/amd/sb600/ac97.c +++ b/southbridge/amd/sb600/ac97.c @@ -38,7 +38,7 @@ struct device_operations ac97audio = { .device = PCI_DEVICE_ID_ATI_SB600_ACI}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -52,7 +52,7 @@ struct device_operations ac97modem = { .device = PCI_DEVICE_ID_ATI_SB600_MCI}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/sb600/hda.c b/southbridge/amd/sb600/hda.c index fff3d05ef558..0aa949bdf959 100644 --- a/southbridge/amd/sb600/hda.c +++ b/southbridge/amd/sb600/hda.c @@ -279,7 +279,7 @@ struct device_operations sb600_hda = { {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_HDA}}}, .constructor = default_device_constructor, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/sb600/ide.c b/southbridge/amd/sb600/ide.c index 19116c15f79f..d7faa2c05c47 100644 --- a/southbridge/amd/sb600/ide.c +++ b/southbridge/amd/sb600/ide.c @@ -70,7 +70,7 @@ struct device_operations sb600_ide = { {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_IDE}}}, .constructor = default_device_constructor, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/sb600/lpc.c b/southbridge/amd/sb600/lpc.c index e95ed178d439..18a260b26eb0 100644 --- a/southbridge/amd/sb600/lpc.c +++ b/southbridge/amd/sb600/lpc.c @@ -213,7 +213,7 @@ struct device_operations sb600_lpc = { .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = sb600_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = sb600_lpc_enable_resources, diff --git a/southbridge/amd/sb600/pci.c b/southbridge/amd/sb600/pci.c index fd05096af3b9..87920f25d714 100644 --- a/southbridge/amd/sb600/pci.c +++ b/southbridge/amd/sb600/pci.c @@ -130,7 +130,7 @@ struct device_operations sb600_pci = { .device = PCI_DEVICE_ID_ATI_SB600_PCI}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, diff --git a/southbridge/amd/sb600/sata.c b/southbridge/amd/sb600/sata.c index cd0127d9cc97..b1d081853abc 100644 --- a/southbridge/amd/sb600/sata.c +++ b/southbridge/amd/sb600/sata.c @@ -192,7 +192,7 @@ struct device_operations sb600_sata = { {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_SATA}}}, .constructor = default_device_constructor, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/sb600/sm.c b/southbridge/amd/sb600/sm.c index 7528d1dc6b16..823f1cce3723 100644 --- a/southbridge/amd/sb600/sm.c +++ b/southbridge/amd/sb600/sm.c @@ -395,7 +395,7 @@ struct device_operations sb600_sm = { .device = PCI_DEVICE_ID_ATI_SB600_SM}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = sb600_sm_read_resources, .phase4_set_resources = sb600_sm_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/amd/sb600/usb.c b/southbridge/amd/sb600/usb.c index 214d953ad4bf..b2a4698ef51c 100644 --- a/southbridge/amd/sb600/usb.c +++ b/southbridge/amd/sb600/usb.c @@ -205,7 +205,7 @@ struct device_operations sb600_usb2 = { .device = PCI_DEVICE_ID_ATI_SB600_USB2}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = usb_set_resources, .phase5_enable_resources = pci_dev_enable_resources, diff --git a/southbridge/intel/i82371eb/i82371eb.c b/southbridge/intel/i82371eb/i82371eb.c index 341c4af007b5..fde4f03fafdc 100644 --- a/southbridge/intel/i82371eb/i82371eb.c +++ b/southbridge/intel/i82371eb/i82371eb.c @@ -90,7 +90,6 @@ struct device_operations i82371eb_isa = { .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = 0, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = i82371eb_isa_init, .ops_pci = &pci_dev_ops_pci, @@ -103,7 +102,6 @@ struct device_operations i82371eb_ide = { .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = 0, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = i82371eb_ide_init, .ops_pci = &pci_dev_ops_pci, @@ -116,7 +114,6 @@ struct device_operations i82371eb_acpi = { .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = 0, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = i82371eb_acpi_init, .ops_pci = &pci_dev_ops_pci, diff --git a/superio/ite/it8712f/superio.c b/superio/ite/it8712f/superio.c index c0e1c4a47fcf..bf0fe0fa749a 100644 --- a/superio/ite/it8712f/superio.c +++ b/superio/ite/it8712f/superio.c @@ -105,10 +105,10 @@ static void it8712f_pnp_enable(struct device * dev) static void it8712f_setup_scan_bus(struct device *dev); struct device_operations it8712f_ops = { - .phase2_setup_scan_bus = it8712f_setup_scan_bus, + .phase3_chip_setup_dev = it8712f_setup_scan_bus, + .phase3_enable = it8712f_pnp_enable_resources, .phase4_read_resources = pnp_read_resources, .phase4_set_resources = it8712f_pnp_set_resources, - .phase4_enable_disable = it8712f_pnp_enable_resources, .phase5_enable_resources = it8712f_pnp_enable, .phase6_init = it8712f_init, }; diff --git a/superio/winbond/w83627hf/superio.c b/superio/winbond/w83627hf/superio.c index 47079431ba92..5d415ed3a8db 100644 --- a/superio/winbond/w83627hf/superio.c +++ b/superio/winbond/w83627hf/superio.c @@ -189,12 +189,12 @@ void w83627hf_pnp_enable(struct device * dev) pnp_exit_ext_func_mode(dev); } } -static void phase2_setup_scan_bus(struct device *dev); +static void phase3_chip_setup_dev(struct device *dev); struct device_operations w83627hf_ops = { - .phase2_setup_scan_bus = phase2_setup_scan_bus, + .phase3_chip_setup_dev = phase3_chip_setup_dev, + .phase3_enable = w83627hf_pnp_enable_resources, .phase4_read_resources = pnp_read_resources, .phase4_set_resources = w83627hf_pnp_set_resources, - .phase4_enable_disable = w83627hf_pnp_enable_resources, .phase5_enable_resources = w83627hf_pnp_enable, .phase6_init = w83627hf_init, }; @@ -215,7 +215,7 @@ static struct pnp_info pnp_dev_info[] = { }; -static void phase2_setup_scan_bus(struct device *dev) +static void phase3_chip_setup_dev(struct device *dev) { pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } |