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Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index d01fdd635251..2c9a548ae0ff 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -8,9 +8,6 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw1" = "GPP_C"
register "pmc_gpe0_dw2" = "GPP_D"
- # Enable heci1 communication
- register "HeciEnabled" = "1"
-
# FSP configuration
register "SaGv" = "SaGv_Enabled"