diff options
Diffstat (limited to 'src/mainboard/system76/tgl-h/variants/gaze16-3050')
8 files changed, 435 insertions, 0 deletions
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/board_info.txt b/src/mainboard/system76/tgl-h/variants/gaze16-3050/board_info.txt new file mode 100644 index 000000000000..6555d4d96054 --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/board_info.txt @@ -0,0 +1,2 @@ +Board name: gaze16 +Release year: 2021 diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt b/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt Binary files differnew file mode 100644 index 000000000000..297522723cbb --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c new file mode 100644 index 000000000000..60b82de86fc1 --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c @@ -0,0 +1,281 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <variant/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKE# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7 + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_NC(GPD9, NONE), // PCH_SLP_WLAN# (100k pull-down) + PAD_NC(GPD10, NONE), // SLP_S5# (100k pull-down) + PAD_NC(GPD11, NONE), + PAD_NC(GPD12, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_AD0 + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_AD1 + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_AD2 + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_AD3 + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_FRAME# + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_KBC + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_NC(GPP_A9, NONE), + PAD_CFG_GPI(GPP_A10, UP_20K, DEEP), // SERIRQ + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_B1, NONE), + PAD_NC(GPP_B2, NONE), + PAD_CFG_GPO(GPP_B3, 1, DEEP), // EC_BT_EN + PAD_NC(GPP_B4, NONE), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GFX_CLKREQ0# + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // SSD2_CLKREQ4# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ5# + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_CFG_GPO(GPP_B15, 1, DEEP), // SSD_PWR_EN# + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPI(GPP_B18, NONE, DEEP), // GSPI0_MOSI + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPI(GPP_B23, NONE, DEEP), // SML1_ALERT# + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT + PAD_CFG_GPI(GPP_C2, NONE, DEEP), // CNVI_WAKE# + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_CFG_GPI(GPP_C5, NONE, DEEP), // SML0_ALERT# + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET + PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPI(GPP_C11, NONE, DEEP), // BOARD_ID3 + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_CFG_GPI(GPP_C14, NONE, DEEP), // GPC14_RTD3 + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, PWROK, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, PWROK, NF1), // I2C_SCL_TP + PAD_CFG_GPI(GPP_C18, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_C19, NONE, DEEP), // SWI# + //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_NC(GPP_C22, NONE), + PAD_CFG_GPI(GPP_C23, NONE, DEEP), // SMI# + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), // SML1_CLK + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2), // CNVI_RF_RST# + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // SML0_DATA + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), // SML1_DATA + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1 + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI# + PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0 + PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), // DEVSLP1 + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# + PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# + PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3# + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_CFG_GPO(GPP_F2, 1, PLTRST), // LAN_RTD3# + PAD_CFG_GPO(GPP_F3, 1, DEEP), // GPP_LAN_RST# + PAD_CFG_GPO(GPP_F4, 1, DEEP), // SATA_PWR_EN + PAD_CFG_GPO(GPP_F5, 1, DEEP), // 1P05_CTRL + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + //PAD_CFG_GPO(GPP_F8, 1, DEEP), // DGPU_RST#_PCH + //PAD_CFG_GPO(GPP_F9, 1, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC + PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD + PAD_CFG_GPO(GPP_F12, 1, DEEP), // PCH_WLAN_EN + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // SKTOCC# + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPO(GPP_F17, 1, DEEP), // SB_BLON + PAD_NC(GPP_F18, NONE), + //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + PAD_NC(GPP_F22, NONE), // VNN_CTRL + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_CFG_GPI(GPP_G1, NONE, DEEP), // CNVI_DET# + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_CFG_GPI(GPP_G9, NONE, DEEP), // GPP_G9 + PAD_NC(GPP_G10, NONE), + PAD_CFG_GPI(GPP_G11, NONE, DEEP), // GPP_G11 + PAD_NC(GPP_G12, NONE), + _PAD_CFG_STRUCT(GPP_G13, 0x44001300, 0x3c00), // GPP_G13 + PAD_NC(GPP_G14, NONE), + PAD_NC(GPP_G15, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CARD_CLKREQ7# + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // WLAN_CLKREQ8# + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ9# + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_CFG_GPI(GPP_H6, NONE, DEEP), // SB_KBCRST# + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_GPI(GPP_H10, NONE, DEEP), // SML_2CLK + PAD_CFG_GPI(GPP_H11, NONE, DEEP), // SML_2DATA + PAD_CFG_GPI(GPP_H12, NONE, DEEP), // SML_2ALERT# + PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML_3CLK + PAD_CFG_GPI(GPP_H14, NONE, DEEP), // SML_3DATA + PAD_CFG_GPI(GPP_H15, NONE, PLTRST), // SML_3ALERT# + PAD_CFG_GPI(GPP_H16, NONE, DEEP), // SML_4CLK + PAD_CFG_GPO(GPP_H17, 1, DEEP), // SSD2_PWR_EN# + PAD_CFG_GPI(GPP_H18, NONE, DEEP), // SML_4ALERT# + PAD_CFG_GPI(GPP_H19, NONE, DEEP), // PCH_FLASH_I2C_SDA + PAD_CFG_GPI(GPP_H20, NONE, DEEP), // PCH_FLASH_I2C_SCL + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_CFG_GPO(GPP_H23, 1, DEEP), // M2_SSD_RST# + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1), // PMC_ALERT# + PAD_CFG_GPI(GPP_I1, NONE, DEEP), // GPU_EVENT# + PAD_NC(GPP_I2, NONE), + PAD_NC(GPP_I3, NONE), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), // HDMI_CTRLDATA + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_CFG_GPO(GPP_I9, 1, DEEP), // M2_SSD2_RST# + PAD_NC(GPP_I10, NONE), + PAD_CFG_GPI(GPP_I11, NONE, PLTRST), // USB_OC4# + PAD_CFG_GPI(GPP_I12, NONE, PLTRST), // USB_OC5# + PAD_CFG_GPI(GPP_I13, NONE, PLTRST), // USB_OC6# + PAD_CFG_GPI(GPP_I14, NONE, PLTRST), // USB_OC7# + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J8, NONE, PLTRST), // GPIO4_GC6_NVDD_EN_R + PAD_NC(GPP_J9, NONE), + + /* ------- GPIO Group GPP_K ------- */ + PAD_CFG_GPO(GPP_K0, 0, DEEP), // DGPU_OVRM + PAD_NC(GPP_K1, NONE), + PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R + PAD_NC(GPP_K3, NONE), + PAD_NC(GPP_K4, NONE), + PAD_NC(GPP_K5, NONE), + PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1), // EDP_HPD + PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), // HDMI_HPD + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + _PAD_CFG_STRUCT(GPP_K10, 0x46880100, 0x0000), // DGPU_MDP_HPD + PAD_CFG_GPI(GPP_K11, DN_20K, DEEP), // GC6_FB_EN_PCH + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), // 100k pull-down + PAD_NC(GPP_R8, NONE), + PAD_NC(GPP_R9, NONE), + PAD_NC(GPP_R10, NONE), + PAD_NC(GPP_R11, NONE), + PAD_CFG_GPI_INT(GPP_R12, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_NC(GPP_R13, NONE), + PAD_NC(GPP_R14, NONE), + PAD_NC(GPP_R15, NONE), + PAD_NC(GPP_R16, NONE), + PAD_NC(GPP_R17, NONE), + PAD_NC(GPP_R18, NONE), + PAD_NC(GPP_R19, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_CFG_GPI(GPP_S6, NONE, DEEP), // DMIC_CLK_PCH + PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c new file mode 100644 index 000000000000..8c97e7f45eab --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <variant/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c new file mode 100644 index 000000000000..35c27a150f70 --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x15585017, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15585017), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), +}; + +const u32 pc_beep_verbs[] = { + // Adjust mic coefficient + 0x02050007, + 0x02040202, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb new file mode 100644 index 000000000000..32f0805ac0df --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -0,0 +1,75 @@ +chip soc/intel/tigerlake + device domain 0 on + subsystemid 0x1558 0x5015 inherit + + device ref peg1 on + # PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU) + register "PcieClkSrcUsage[0]" = "0x42" + register "PcieClkSrcClkReq[0]" = "0" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH + register "enable_delay_ms" = "16" + register "enable_off_delay_ms" = "4" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "4" + register "srcclk_pin" = "0" # GFX_CLKREQ0# + device generic 0 on end + end + end + device ref peg0 on + # PCIe PEG0 x4, Clock 4 (SSD2) + register "PcieClkSrcUsage[4]" = "0x40" + register "PcieClkSrcClkReq[4]" = "4" + end + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right) + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left) + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left) + end + device ref sata on + register "SataPortsEnable[0]" = "1" # HDD (SATA0B) + register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A) + end + device ref pcie_rp5 on + # PCIe root port #5 x1, Clock 5 (GLAN) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[5]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + end + device ref pcie_rp7 on + # PCIe root port #7 x1, Clock 7 (CARD) + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieClkSrcUsage[7]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + end + device ref pcie_rp8 on + # PCIe root port #8 x1, Clock 8 (WLAN) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[8]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieRpSlotImplemented[7]" = "1" + end + device ref pcie_rp9 on + # PCIe root port #9 x4, Clock 9 (SSD1) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[9]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieRpSlotImplemented[8]" = "1" + end + end +end diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c new file mode 100644 index 000000000000..9d985630d0f8 --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->PchLegacyIoLowLatency = 1; + + // PEG0 Config + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // PEG2 Config + params->CpuPcieRpAdvancedErrorReporting[2] = 0; + params->CpuPcieRpLtrEnable[2] = 1; + params->CpuPcieRpPtmEnabled[2] = 0; + + // Remap PEG2 as PEG1 + params->CpuPcieRpFunctionSwap = 1; +} diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/romstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/romstage.c new file mode 100644 index 000000000000..f28c0c23d36c --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/romstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/romstage.h> + +void variant_memory_init_params(FSPM_UPD *mupd) +{ + // Enable M.2 PCIE 4.0 and PEG2 + mupd->FspmConfig.CpuPcieRpEnableMask = 0x5; +} |