diff options
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index fee71052454f..59dab58bb834 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -133,6 +133,23 @@ struct soc_intel_tigerlake_config { uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; + + /* + * SATA Port Enable Dito Config. + * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). + */ + uint8_t SataPortsEnableDitoConfig[8]; + + /* SataPortsDmVal is the DITO multiplier. Default is 15. */ + uint8_t SataPortsDmVal[8]; + /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ + uint16_t SataPortsDitoVal[8]; + /* Audio related */ uint8_t PchHdaDspEnable; uint8_t PchHdaAudioLinkHdaEnable; @@ -337,12 +354,6 @@ struct soc_intel_tigerlake_config { */ uint8_t DmiPwrOptimizeDisable; - /* - * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. - * Default 0. Setting this to 1 disables the SATA Power Optimizer. - */ - uint8_t SataPwrOptimizeDisable; - /* structure containing various settings for PCH FIVRs */ struct { bool configure_ext_fivr; |