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-rw-r--r--src/soc/intel/tigerlake/chip.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index fb0d8278b8bd..59651d58b39d 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -248,6 +248,8 @@ struct soc_intel_tigerlake_config {
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
+ /* Implemented as slot or built-in? */
+ uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
/* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */