diff options
Diffstat (limited to 'src/soc/intel')
44 files changed, 575 insertions, 37 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 10f2d3cc0fbc..3473b0643af2 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -483,6 +483,19 @@ struct soc_intel_alderlake_config { IGD_SM_60MB = 0xFE, } igd_dvmt50_pre_alloc; + enum { + IGD_AP_SZ_128MB = 0x00, + IGD_AP_SZ_256MB = 0x01, + IGD_AP_SZ_512MB = 0x02, + /* + * Values below require use of above 4G MMIO, + * otherwise FSP will hang + */ + IGD_AP_SZ_4G_512MB = 0x03, + IGD_AP_SZ_4G_1024MB = 0x07, + IGD_AP_SZ_4G_2048MB = 0x15, + } igd_aperture_size; + bool skip_ext_gfx_scan; bool eist_enable; bool enable_c6dram; diff --git a/src/soc/intel/alderlake/include/soc/cfr.h b/src/soc/intel/alderlake/include/soc/cfr.h new file mode 100644 index 000000000000..1e54d585f121 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/cfr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * CFR enums and structs which are used to control SoC settings. + */ + +#ifndef _ALDERLAKE_CFR_H_ +#define _ALDERLAKE_CFR_H_ + +#include <drivers/option/cfr_frontend.h> +#include <soc/soc_chip.h> + +/* FSP hyperthreading */ +static const struct sm_object hyper_threading = SM_DECLARE_ENUM({ + .opt_name = "hyper_threading", + .ui_name = "Hyper-Threading", + .ui_helptext = "Enable or disable Hyper-Threading", + .default_value = CONFIG(FSP_HYPERTHREADING), + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* IGD Aperture Size */ +static const struct sm_object igd_aperture = SM_DECLARE_ENUM({ + .opt_name = "igd_aperture_size", + .ui_name = "IGD Aperture Size", + .ui_helptext = "Select the Aperture Size", + .default_value = IGD_AP_SZ_256MB, + .values = (const struct sm_enum_value[]) { + { " 128 MB", IGD_AP_SZ_128MB }, + { " 256 MB", IGD_AP_SZ_256MB }, +#if CONFIG(ALWAYS_ALLOW_ABOVE_4G_ALLOCATION) + { " 512 MB (4G MMIO)", IGD_AP_SZ_4G_512MB }, + { "1024 MB (4G MMIO)", IGD_AP_SZ_4G_1024MB }, + { "2048 MB (4G MMIO)", IGD_AP_SZ_4G_2048MB }, +#else + { " 512 MB", IGD_AP_SZ_512MB }, +#endif + SM_ENUM_VALUE_END }, +}); + +/* IGD DVMT pre-allocated memory */ +static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({ + .opt_name = "igd_dvmt_prealloc", + .ui_name = "IGD DVMT Size", + .ui_helptext = "Size of memory preallocated for internal graphics", + .default_value = IGD_SM_60MB, + .values = (const struct sm_enum_value[]) { + { " 32 MB", IGD_SM_32MB }, + { " 60 MB", IGD_SM_60MB }, + { " 64 MB", IGD_SM_64MB }, + { " 96 MB", IGD_SM_96MB }, + { "128 MB", IGD_SM_128MB }, + { "160 MB", IGD_SM_160MB }, + SM_ENUM_VALUE_END }, +}); + +/* Legacy 8254 Timer */ +static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({ + .opt_name = "legacy_8254_timer", + .ui_name = "Legacy 8254 Timer", + .ui_helptext = "Enable the legacy 8254 timer by disabling clock gating.", + .default_value = 0, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* S0ix Enable */ +static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({ + .opt_name = "s0ix_enable", + .ui_name = "Modern Standby (S0ix)", + .ui_helptext = "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* VT-d */ +static const struct sm_object vtd = SM_DECLARE_ENUM({ + .opt_name = "vtd", + .ui_name = "VT-d", + .ui_helptext = "Enable or disable Intel VT-d (virtualization)", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +#endif /* _ALDERLAKE_CFR_H_ */ diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 427de4d7c3bf..6ab8bb3e5071 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -134,7 +134,8 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); if (m_cfg->InternalGfx) { /* IGD is enabled, set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB; + m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB); + m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB); /* DP port config */ m_cfg->DdiPortAConfig = config->ddi_portA_config; m_cfg->DdiPortBConfig = config->ddi_portB_config; @@ -315,7 +316,7 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS; - m_cfg->VtdDisable = 0; + m_cfg->VtdDisable = !get_uint_option("vtd", 1); m_cfg->VtdIopEnable = !m_cfg->VtdDisable; m_cfg->VtdIgdEnable = m_cfg->InternalGfx; m_cfg->VtdIpuEnable = m_cfg->SaIpuEnable; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index c5553780ea59..943573fff75d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -693,6 +693,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) memcpy(silconfig->SataPortsHotPlug, cfg->sata_ports_hot_plug, sizeof(silconfig->SataPortsHotPlug)); + cfg->lpss_s0ix_enable = get_uint_option("s0ix_enable", cfg->lpss_s0ix_enable); silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; /* Disable monitor mwait since it is broken due to a hardware bug diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 591abbeaaed4..f4785bb36504 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -36,6 +36,21 @@ enum chip_pl2_4_cfg { value_not_set /* vr_config internal use only */ }; +/* Gfx related */ +enum igd_dvmt50_pre_alloc { + IGD_SM_0MB = 0x00, + IGD_SM_32MB = 0x01, + IGD_SM_64MB = 0x02, + IGD_SM_96MB = 0x03, + IGD_SM_128MB = 0x04, +}; + +enum igd_aperture_size { + IGD_AP_SZ_128MB = 0x00, + IGD_AP_SZ_256MB = 0x01, + IGD_AP_SZ_512MB = 0x02, +}; + struct soc_intel_cannonlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; diff --git a/src/soc/intel/cannonlake/include/soc/cfr.h b/src/soc/intel/cannonlake/include/soc/cfr.h index ae61799a68f8..15262567039c 100644 --- a/src/soc/intel/cannonlake/include/soc/cfr.h +++ b/src/soc/intel/cannonlake/include/soc/cfr.h @@ -8,6 +8,7 @@ #define CANNONLAKE_CFR_H #include <drivers/option/cfr_frontend.h> +#include <soc/soc_chip.h> /* FSP hyperthreading */ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({ @@ -26,11 +27,11 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({ .opt_name = "igd_aperture_size", .ui_name = "IGD Aperture Size", .ui_helptext = "Select the Aperture Size", - .default_value = 1, + .default_value = IGD_AP_SZ_256MB, .values = (const struct sm_enum_value[]) { - { "128 MB", 0 }, - { "256 MB", 1 }, - { "512 MB", 2 }, + { "128 MB", IGD_AP_SZ_128MB }, + { "256 MB", IGD_AP_SZ_256MB }, + { "512 MB", IGD_AP_SZ_512MB }, SM_ENUM_VALUE_END }, }); @@ -39,12 +40,12 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({ .opt_name = "igd_dvmt_prealloc", .ui_name = "IGD DVMT Size", .ui_helptext = "Size of memory preallocated for internal graphics", - .default_value = 2, + .default_value = IGD_SM_64MB, .values = (const struct sm_enum_value[]) { - { "32 MB", 1 }, - { "64 MB", 2 }, - { "96 MB", 3 }, - { "128 MB", 4 }, + { "32 MB", IGD_SM_32MB }, + { "64 MB", IGD_SM_64MB }, + { "96 MB", IGD_SM_96MB }, + { "128 MB", IGD_SM_128MB }, SM_ENUM_VALUE_END }, }); diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 74812f31bfbb..a8523f14aba3 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -14,6 +14,7 @@ #include <soc/pci_devs.h> #include <soc/pcie.h> #include <soc/romstage.h> +#include <soc/soc_chip.h> #include <types.h> #include "../chip.h" @@ -37,8 +38,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) { /* Set IGD stolen size to 64MB. */ m_cfg->InternalGfx = 1; - m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", 2); - m_cfg->ApertureSize = get_uint_option("igd_aperture_size", 1); + m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_64MB); + m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB); } else { m_cfg->InternalGfx = 0; m_cfg->IgdDvmt50PreAlloc = 0; diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 3abd90744001..7aada2007991 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -442,6 +442,7 @@ static const unsigned short wifi_pci_device_ids[] = { PCI_DID_INTEL_MTL_CNVI_WIFI_1, PCI_DID_INTEL_MTL_CNVI_WIFI_2, PCI_DID_INTEL_MTL_CNVI_WIFI_3, + PCI_DID_INTEL_ARL_CNVI_WIFI, PCI_DID_INTEL_CML_LP_CNVI_WIFI, PCI_DID_INTEL_CML_H_CNVI_WIFI, PCI_DID_INTEL_CNL_LP_CNVI_WIFI, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 1602126890e6..a8ee838710b1 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -40,6 +40,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index d1548a1fcb31..ce998e4b565a 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -463,3 +463,11 @@ config CSE_RESET_CLEAR_EC_AP_IDLE_FLAG Select this if the variant is a Chromebox/base. This allows AP to direct EC to clear AP_IDLE flag before triggering reset to make sure AP can boot up after reset. + +config CSE_DEFAULT_CFR_OPTION_STATE_DISABLED + bool + default n + help + Mainboards can select this if using the CFR option backend to configure + the ME operational state and want the default state to be disabled. + If not selected, the default state will be enabled. diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ef1105cfdf9c..58999c0b9f1b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1532,6 +1532,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_CSE0, PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, + PCI_DID_INTEL_ARL_CSE0, PCI_DID_INTEL_APL_CSE0, PCI_DID_INTEL_GLK_CSE0, PCI_DID_INTEL_CNL_CSE0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index bd8c9acabb12..f36ab088aafe 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -53,6 +53,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_AUDIO_6, PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, + PCI_DID_INTEL_ARL_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 8cff0707b6a7..b5ee53a71593 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -577,6 +577,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LWB_SPI_SUPER, PCI_DID_INTEL_MCC_SPI0, PCI_DID_INTEL_MTL_HWSEQ_SPI, + PCI_DID_INTEL_ARL_HWSEQ_SPI, PCI_DID_INTEL_RPP_S_HWSEQ_SPI, PCI_DID_INTEL_SPR_HWSEQ_SPI, PCI_DID_INTEL_TGP_SPI0, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index b2229152c452..165727ef0ee7 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -365,6 +365,8 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_P_GT2_3, PCI_DID_INTEL_MTL_P_GT2_4, PCI_DID_INTEL_MTL_P_GT2_5, + PCI_DID_INTEL_ARL_H_GT2_1, + PCI_DID_INTEL_ARL_H_GT2_2, PCI_DID_INTEL_APL_IGD_HD_505, PCI_DID_INTEL_APL_IGD_HD_500, PCI_DID_INTEL_CNL_GT2_ULX_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 028b9eaacf85..f375e0c58d10 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -69,6 +69,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_AUDIO_6, PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, + PCI_DID_INTEL_ARL_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 8097b7402295..dfb14a0ea5a3 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -204,6 +204,12 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_I2C3, PCI_DID_INTEL_MTL_I2C4, PCI_DID_INTEL_MTL_I2C5, + PCI_DID_INTEL_ARL_I2C0, + PCI_DID_INTEL_ARL_I2C1, + PCI_DID_INTEL_ARL_I2C2, + PCI_DID_INTEL_ARL_I2C3, + PCI_DID_INTEL_ARL_I2C4, + PCI_DID_INTEL_ARL_I2C5, PCI_DID_INTEL_APL_I2C0, PCI_DID_INTEL_APL_I2C1, PCI_DID_INTEL_APL_I2C2, diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h index c240b769f36c..fe9af039a697 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfr.h +++ b/src/soc/intel/common/block/include/intelblocks/cfr.h @@ -16,7 +16,7 @@ static const struct sm_object me_state = SM_DECLARE_ENUM({ .opt_name = "me_state", .ui_name = "Intel Management Engine", .ui_helptext = "Enable or disable the Intel Management Engine", - .default_value = 0, + .default_value = CONFIG(CSE_DEFAULT_CFR_OPTION_STATE_DISABLED), .values = (const struct sm_enum_value[]) { { "Disabled", 1 }, { "Enabled", 0 }, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 7ed01c6f852c..960a26f7d3f0 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -263,6 +263,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_ESPI_5, PCI_DID_INTEL_MTL_ESPI_6, PCI_DID_INTEL_MTL_ESPI_7, + PCI_DID_INTEL_ARL_H_ESPI_0, + PCI_DID_INTEL_ARL_H_ESPI_1, + PCI_DID_INTEL_ARL_U_ESPI_0, PCI_DID_INTEL_RPP_P_ESPI_0, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index c32982f30eea..1986e4ce4f42 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -142,6 +142,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_P2SB, PCI_DID_INTEL_LNL_P2SB, PCI_DID_INTEL_MTL_SOC_P2SB, + PCI_DID_INTEL_ARL_SOC_P2SB, PCI_DID_INTEL_RPP_P_P2SB, PCI_DID_INTEL_APL_P2SB, PCI_DID_INTEL_GLK_P2SB, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index a2db27619539..1b3e148f152d 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -119,6 +119,15 @@ static const unsigned short pcie_device_ids[] = { PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12, + PCI_DID_INTEL_ARL_SOC_PCIE_RP1, + PCI_DID_INTEL_ARL_SOC_PCIE_RP2, + PCI_DID_INTEL_ARL_SOC_PCIE_RP3, + PCI_DID_INTEL_ARL_SOC_PCIE_RP4, + PCI_DID_INTEL_ARL_SOC_PCIE_RP5, + PCI_DID_INTEL_ARL_SOC_PCIE_RP6, + PCI_DID_INTEL_ARL_SOC_PCIE_RP7, + PCI_DID_INTEL_ARL_SOC_PCIE_RP8, + PCI_DID_INTEL_ARL_SOC_PCIE_RP9, PCI_DID_INTEL_LWB_PCIE_RP1, PCI_DID_INTEL_LWB_PCIE_RP2, PCI_DID_INTEL_LWB_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 50c394504428..dbdf2fe5fd64 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -118,6 +118,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SOC_PMC, PCI_DID_INTEL_MTL_IOE_M_PMC, PCI_DID_INTEL_MTL_IOE_P_PMC, + PCI_DID_INTEL_ARL_SOC_PMC, PCI_DID_INTEL_RPP_P_PMC, PCI_DID_INTEL_DNV_PMC, PCI_DID_INTEL_LWB_PMC, diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index ca61c682dfb7..ae51efa95c46 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -36,6 +36,7 @@ struct device_operations sata_ops = { static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SATA, + PCI_DID_INTEL_ARL_SATA, PCI_DID_INTEL_RPP_P_SATA_1, PCI_DID_INTEL_RPP_P_SATA_2, PCI_DID_INTEL_RPP_S_SATA, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 87b44f547b6f..fc8c0aff09af 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -54,6 +54,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_SMBUS, PCI_DID_INTEL_LNL_SMBUS, PCI_DID_INTEL_MTL_SMBUS, + PCI_DID_INTEL_ARL_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, PCI_DID_INTEL_RPP_S_SMBUS, PCI_DID_INTEL_APL_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 5b45facd4c46..1dc12d0b4592 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -141,6 +141,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_GSPI0, PCI_DID_INTEL_MTL_GSPI1, PCI_DID_INTEL_MTL_GSPI2, + PCI_DID_INTEL_ARL_GSPI0, + PCI_DID_INTEL_ARL_GSPI1, + PCI_DID_INTEL_ARL_GSPI2, PCI_DID_INTEL_APL_SPI0, PCI_DID_INTEL_APL_SPI1, PCI_DID_INTEL_APL_SPI2, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index f4eda9790dc4..35777d98ba4b 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -43,6 +43,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_IOE_M_SRAM, PCI_DID_INTEL_MTL_IOE_P_SRAM, PCI_DID_INTEL_MTL_CRASHLOG_SRAM, + PCI_DID_INTEL_ARL_SOC_SRAM, PCI_DID_INTEL_APL_SRAM, PCI_DID_INTEL_GLK_SRAM, PCI_DID_INTEL_CMP_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index bb3b821c4491..b3f8c0c695e7 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -440,6 +440,8 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_MTL_P_ID_3, PCI_DID_INTEL_MTL_P_ID_4, PCI_DID_INTEL_MTL_P_ID_5, + PCI_DID_INTEL_ARL_H_ID_1, + PCI_DID_INTEL_ARL_H_ID_2, PCI_DID_INTEL_GLK_NB, PCI_DID_INTEL_APL_NB, PCI_DID_INTEL_CNL_ID_U, diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c index ab1d4a6b99f2..65eadf33b22f 100644 --- a/src/soc/intel/common/block/tracehub/tracehub.c +++ b/src/soc/intel/common/block/tracehub/tracehub.c @@ -46,6 +46,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_H_TRACEHUB, PCI_DID_INTEL_PTL_U_H_TRACEHUB, PCI_DID_INTEL_MTL_TRACEHUB, + PCI_DID_INTEL_ARL_TRACEHUB, PCI_DID_INTEL_RPL_TRACEHUB, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 839f54ebe5bf..2c1075993adb 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -375,6 +375,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_UART0, PCI_DID_INTEL_MTL_UART1, PCI_DID_INTEL_MTL_UART2, + PCI_DID_INTEL_ARL_UART0, + PCI_DID_INTEL_ARL_UART1, + PCI_DID_INTEL_ARL_UART2, PCI_DID_INTEL_APL_UART0, PCI_DID_INTEL_APL_UART1, PCI_DID_INTEL_APL_UART2, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 3878bf9ada6b..a5a5158789ac 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -32,6 +32,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_H_XDCI, PCI_DID_INTEL_PTL_U_H_XDCI, PCI_DID_INTEL_MTL_XDCI, + PCI_DID_INTEL_ARL_XDCI, PCI_DID_INTEL_APL_XDCI, PCI_DID_INTEL_CNL_LP_XDCI, PCI_DID_INTEL_GLK_XDCI, diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 4892e11e162a..0197f4662673 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -136,6 +136,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_XHCI, PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_MTL_XHCI, + PCI_DID_INTEL_ARL_XHCI, PCI_DID_INTEL_APL_XHCI, PCI_DID_INTEL_CNL_LP_XHCI, PCI_DID_INTEL_GLK_XHCI, diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 408cdcfa46aa..380549451e3b 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -57,6 +57,36 @@ static const struct { { PCI_DID_INTEL_JSL_ID_6, JSL_N6005_10W_CORE, TDP_10W }, }; +/* Gfx related */ +enum igd_dvmt50_pre_alloc { + IGD_SM_0MB = 0x00, + IGD_SM_32MB = 0x01, + IGD_SM_64MB = 0x02, + IGD_SM_96MB = 0x03, + IGD_SM_128MB = 0x04, + IGD_SM_160MB = 0x05, + IGD_SM_4MB = 0xF0, + IGD_SM_8MB = 0xF1, + IGD_SM_12MB = 0xF2, + IGD_SM_16MB = 0xF3, + IGD_SM_20MB = 0xF4, + IGD_SM_24MB = 0xF5, + IGD_SM_28MB = 0xF6, + IGD_SM_36MB = 0xF8, + IGD_SM_40MB = 0xF9, + IGD_SM_44MB = 0xFA, + IGD_SM_48MB = 0xFB, + IGD_SM_52MB = 0xFC, + IGD_SM_56MB = 0xFD, + IGD_SM_60MB = 0xFE, +}; + +enum igd_aperture_size { + IGD_AP_SZ_128MB = 0x00, + IGD_AP_SZ_256MB = 0x01, + IGD_AP_SZ_512MB = 0x02, +}; + struct soc_intel_jasperlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; diff --git a/src/soc/intel/jasperlake/include/soc/cfr.h b/src/soc/intel/jasperlake/include/soc/cfr.h new file mode 100644 index 000000000000..9aca7bb0d002 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/cfr.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * CFR enums and structs which are used to control SoC settings. + */ + +#ifndef _JASPERLAKE_CFR_H_ +#define _JASPERLAKE_CFR_H_ + +#include <drivers/option/cfr_frontend.h> +#include <soc/soc_chip.h> + +/* IGD Aperture Size */ +static const struct sm_object igd_aperture = SM_DECLARE_ENUM({ + .opt_name = "igd_aperture_size", + .ui_name = "IGD Aperture Size", + .ui_helptext = "Select the Aperture Size", + .default_value = IGD_AP_SZ_256MB, + .values = (const struct sm_enum_value[]) { + { " 128 MB", IGD_AP_SZ_128MB }, + { " 256 MB", IGD_AP_SZ_256MB }, + { " 512 MB", IGD_AP_SZ_512MB }, + SM_ENUM_VALUE_END }, +}); + +/* IGD DVMT pre-allocated memory */ +static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({ + .opt_name = "igd_dvmt_prealloc", + .ui_name = "IGD DVMT Size", + .ui_helptext = "Size of memory preallocated for internal graphics", + .default_value = IGD_SM_60MB, + .values = (const struct sm_enum_value[]) { + { " 32 MB", IGD_SM_32MB }, + { " 60 MB", IGD_SM_60MB }, + { " 64 MB", IGD_SM_64MB }, + { " 96 MB", IGD_SM_96MB }, + { "128 MB", IGD_SM_128MB }, + { "160 MB", IGD_SM_160MB }, + SM_ENUM_VALUE_END }, +}); + +/* Legacy 8254 Timer */ +static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({ + .opt_name = "legacy_8254_timer", + .ui_name = "Legacy 8254 Timer", + .ui_helptext = "Enable the legacy 8254 timer by disabling clock gating.", + .default_value = 0, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* S0ix Enable */ +static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({ + .opt_name = "s0ix_enable", + .ui_name = "Modern Standby (S0ix)", + .ui_helptext = "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* VT-d */ +static const struct sm_object vtd = SM_DECLARE_ENUM({ + .opt_name = "vtd", + .ui_name = "VT-d", + .ui_helptext = "Enable or disable Intel VT-d (virtualization)", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +#endif /* _JASPERLAKE_CFR_H_ */ diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 5a06e1234731..b39bd778baf0 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -6,6 +6,7 @@ #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> +#include <option.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pcie.h> @@ -18,12 +19,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, { unsigned int i; - /* - * If IGD is enabled, set IGD stolen size to 60MB. - * Otherwise, skip IGD init in FSP. - */ m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); - m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; + + if (m_cfg->InternalGfx) { + /* IGD is enabled, set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB); + m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB); + } else { + /* IGD is disabled, skip IGD init in FSP. */ + m_cfg->IgdDvmt50PreAlloc = 0; + } m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->SaGv = config->SaGv; @@ -100,7 +105,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT; /* VT-d config */ - m_cfg->VtdDisable = 0; + m_cfg->VtdDisable = !get_uint_option("vtd", 1); m_cfg->VtdIopEnable = 0x1; if (m_cfg->InternalGfx) { diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 405698962d6a..4744abb2c7c7 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -22,6 +22,7 @@ static struct { { CPUID_METEORLAKE_A0_2, "MeteorLake A0" }, { CPUID_METEORLAKE_B0, "MeteorLake B0" }, { CPUID_METEORLAKE_C0, "MeteorLake C0" }, + { CPUID_ARROWLAKE_H_A0, "ArrowLake-H A0" }, }; static struct { @@ -34,6 +35,8 @@ static struct { { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" }, + { PCI_DID_INTEL_ARL_H_ID_1, "ArrowLake-H" }, + { PCI_DID_INTEL_ARL_H_ID_2, "ArrowLake-H" }, }; static struct { @@ -48,6 +51,9 @@ static struct { { PCI_DID_INTEL_MTL_ESPI_5, "MeteorLake SOC" }, { PCI_DID_INTEL_MTL_ESPI_6, "MeteorLake SOC" }, { PCI_DID_INTEL_MTL_ESPI_7, "MeteorLake SOC" }, + { PCI_DID_INTEL_ARL_H_ESPI_0, "ArrowLake-H SOC" }, + { PCI_DID_INTEL_ARL_H_ESPI_1, "ArrowLake-H SOC" }, + { PCI_DID_INTEL_ARL_U_ESPI_0, "ArrowLake-U SOC" }, }; static struct { @@ -60,6 +66,8 @@ static struct { { PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_4, "Meteorlake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" }, + { PCI_DID_INTEL_ARL_H_GT2_1, "ArrowLake-H GT2" }, + { PCI_DID_INTEL_ARL_H_GT2_2, "ArrowLake-H GT2" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 2c93aac69dfc..88aaaf643522 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -65,6 +65,8 @@ static const struct { { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W }, { PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W }, { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_H_ID_2, MTL_P_682_482_CORE, TDP_28W }, }; /* Types of display ports */ diff --git a/src/soc/intel/meteorlake/include/soc/cfr.h b/src/soc/intel/meteorlake/include/soc/cfr.h new file mode 100644 index 000000000000..c8db514c99cc --- /dev/null +++ b/src/soc/intel/meteorlake/include/soc/cfr.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * CFR enums and structs which are used to control SoC settings. + */ + +#ifndef _METEORLAKE_CFR_H_ +#define _METEORLAKE_CFR_H_ + +#include <drivers/option/cfr_frontend.h> +#include <soc/soc_chip.h> + +/* FSP hyperthreading */ +static const struct sm_object hyper_threading = SM_DECLARE_ENUM({ + .opt_name = "hyper_threading", + .ui_name = "Hyper-Threading", + .ui_helptext = "Enable or disable Hyper-Threading", + .default_value = CONFIG(FSP_HYPERTHREADING), + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* IGD DVMT pre-allocated memory */ +static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({ + .opt_name = "igd_dvmt_prealloc", + .ui_name = "IGD DVMT Size", + .ui_helptext = "Size of memory preallocated for internal graphics", + .default_value = IGD_SM_128MB, + .values = (const struct sm_enum_value[]) { + { " 32 MB", IGD_SM_32MB }, + { " 64 MB", IGD_SM_64MB }, + { " 96 MB", IGD_SM_96MB }, + { "128 MB", IGD_SM_128MB }, + { "160 MB", IGD_SM_160MB }, + SM_ENUM_VALUE_END }, +}); + +/* Legacy 8254 Timer */ +static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({ + .opt_name = "legacy_8254_timer", + .ui_name = "Legacy 8254 Timer", + .ui_helptext = "Enable the legacy 8254 timer by disabling clock gating.", + .default_value = 0, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* S0ix Enable */ +static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({ + .opt_name = "s0ix_enable", + .ui_name = "Modern Standby (S0ix)", + .ui_helptext = "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* VT-d */ +static const struct sm_object vtd = SM_DECLARE_ENUM({ + .opt_name = "vtd", + .ui_name = "VT-d", + .ui_helptext = "Enable or disable Intel VT-d (virtualization)", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +#endif /* _METEORLAKE_CFR_H_ */ diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 8e49afa10184..190cb7308508 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -118,7 +118,7 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD); if (m_cfg->InternalGfx) { /* IGD is enabled, set IGD stolen size to 128MB. */ - m_cfg->IgdDvmt50PreAlloc = IGD_SM_128MB; + m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_128MB); /* DP port config */ m_cfg->DdiPortAConfig = config->ddi_port_A_config; m_cfg->DdiPortBConfig = config->ddi_port_B_config; @@ -354,7 +354,7 @@ static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { - m_cfg->VtdDisable = 0; + m_cfg->VtdDisable = !get_uint_option("vtd", 1); m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index d12c3eb21848..8edb08eb3544 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -30,6 +30,21 @@ enum skylake_i2c_voltage { I2C_VOLTAGE_1V8 }; +/* Gfx related */ +enum igd_dvmt50_pre_alloc { + IGD_SM_0MB = 0x00, + IGD_SM_32MB = 0x01, + IGD_SM_64MB = 0x02, + IGD_SM_96MB = 0x03, + IGD_SM_128MB = 0x04, +}; + +enum igd_aperture_size { + IGD_AP_SZ_128MB = 0x00, + IGD_AP_SZ_256MB = 0x01, + IGD_AP_SZ_512MB = 0x02, +}; + struct soc_intel_skylake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 8f294f7c8f06..853ad6840e3f 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -199,8 +199,7 @@ static void post_mp_init(void) global_smi_enable_no_pwrbtn(); /* Lock down the SMRAM space. */ - if (CONFIG(HAVE_SMI_HANDLER)) - smm_lock(); + smm_lock(); if (mp_run_on_all_cpus(vmx_configure, NULL) != CB_SUCCESS) failure = true; diff --git a/src/soc/intel/skylake/include/soc/cfr.h b/src/soc/intel/skylake/include/soc/cfr.h index ad5c6f6f53b9..52899015d364 100644 --- a/src/soc/intel/skylake/include/soc/cfr.h +++ b/src/soc/intel/skylake/include/soc/cfr.h @@ -8,6 +8,7 @@ #define SKYLAKE_CFR_H #include <drivers/option/cfr_frontend.h> +#include <soc/soc_chip.h> /* FSP hyperthreading */ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({ @@ -26,11 +27,11 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({ .opt_name = "igd_aperture_size", .ui_name = "IGD Aperture Size", .ui_helptext = "Select the Aperture Size", - .default_value = 1, + .default_value = IGD_AP_SZ_256MB, .values = (const struct sm_enum_value[]) { - { "128 MB", 0 }, - { "256 MB", 1 }, - { "512 MB", 2 }, + { "128 MB", IGD_AP_SZ_128MB }, + { "256 MB", IGD_AP_SZ_256MB }, + { "512 MB", IGD_AP_SZ_512MB }, SM_ENUM_VALUE_END }, }); @@ -39,12 +40,12 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({ .opt_name = "igd_dvmt_prealloc", .ui_name = "IGD DVMT Size", .ui_helptext = "Size of memory preallocated for internal graphics", - .default_value = 2, + .default_value = IGD_SM_64MB, .values = (const struct sm_enum_value[]) { - { "32 MB", 1 }, - { "64 MB", 2 }, - { "96 MB", 3 }, - { "128 MB", 4 }, + { "32 MB", IGD_SM_32MB }, + { "64 MB", IGD_SM_64MB }, + { "96 MB", IGD_SM_96MB }, + { "128 MB", IGD_SM_128MB }, SM_ENUM_VALUE_END }, }); diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index 906301dd1fb8..02123f837a7d 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -116,8 +116,14 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, * * If disabled, don't reserve memory for it. */ - m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? get_uint_option("igd_dvmt_prealloc", 2) : 0; - m_cfg->ApertureSize = get_uint_option("igd_aperture_size", 1); + if (m_cfg->InternalGfx) { + /* IGD is enabled, set IGD stolen size to 64MB. */ + m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_64MB); + m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB); + } else { + /* IGD is disabled, skip IGD init in FSP. */ + m_cfg->IgdDvmt50PreAlloc = 0; + } m_cfg->PrimaryDisplay = config->PrimaryDisplay; } diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 2c0a9b40731d..6f9acb9a9235 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -115,6 +115,42 @@ enum ddi_port_config { DDI_PORT_CFG_MIPI_DSI = 2, }; +enum igd_dvmt50_pre_alloc { + IGD_SM_0MB = 0x00, + IGD_SM_32MB = 0x01, + IGD_SM_64MB = 0x02, + IGD_SM_96MB = 0x03, + IGD_SM_128MB = 0x04, + IGD_SM_160MB = 0x05, + IGD_SM_4MB = 0xF0, + IGD_SM_8MB = 0xF1, + IGD_SM_12MB = 0xF2, + IGD_SM_16MB = 0xF3, + IGD_SM_20MB = 0xF4, + IGD_SM_24MB = 0xF5, + IGD_SM_28MB = 0xF6, + IGD_SM_36MB = 0xF8, + IGD_SM_40MB = 0xF9, + IGD_SM_44MB = 0xFA, + IGD_SM_48MB = 0xFB, + IGD_SM_52MB = 0xFC, + IGD_SM_56MB = 0xFD, + IGD_SM_60MB = 0xFE, +}; + +enum igd_aperture_size { + IGD_AP_SZ_128MB = 0x00, + IGD_AP_SZ_256MB = 0x01, + IGD_AP_SZ_512MB = 0x02, + /* + * Values below require use of above 4G MMIO, + * otherwise FSP will hang + */ + IGD_AP_SZ_4G_512MB = 0x03, + IGD_AP_SZ_4G_1024MB = 0x07, + IGD_AP_SZ_4G_2048MB = 0x15, +}; + struct soc_intel_tigerlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; diff --git a/src/soc/intel/tigerlake/include/soc/cfr.h b/src/soc/intel/tigerlake/include/soc/cfr.h new file mode 100644 index 000000000000..529a4eba794f --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/cfr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * CFR enums and structs which are used to control SoC settings. + */ + +#ifndef _TIGERLAKE_CFR_H_ +#define _TIGERLAKE_CFR_H_ + +#include <drivers/option/cfr_frontend.h> +#include <soc/soc_chip.h> + +/* FSP hyperthreading */ +static const struct sm_object hyper_threading = SM_DECLARE_ENUM({ + .opt_name = "hyper_threading", + .ui_name = "Hyper-Threading", + .ui_helptext = "Enable or disable Hyper-Threading", + .default_value = CONFIG(FSP_HYPERTHREADING), + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* IGD Aperture Size */ +static const struct sm_object igd_aperture = SM_DECLARE_ENUM({ + .opt_name = "igd_aperture_size", + .ui_name = "IGD Aperture Size", + .ui_helptext = "Select the Aperture Size", + .default_value = IGD_AP_SZ_256MB, + .values = (const struct sm_enum_value[]) { + { " 128 MB", IGD_AP_SZ_128MB }, + { " 256 MB", IGD_AP_SZ_256MB }, +#if CONFIG(ALWAYS_ALLOW_ABOVE_4G_ALLOCATION) + { " 512 MB (4G MMIO)", IGD_AP_SZ_4G_512MB }, + { "1024 MB (4G MMIO)", IGD_AP_SZ_4G_1024MB }, + { "2048 MB (4G MMIO)", IGD_AP_SZ_4G_2048MB }, +#else + { " 512 MB", IGD_AP_SZ_512MB }, +#endif + SM_ENUM_VALUE_END }, +}); + +/* IGD DVMT pre-allocated memory */ +static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({ + .opt_name = "igd_dvmt_prealloc", + .ui_name = "IGD DVMT Size", + .ui_helptext = "Size of memory preallocated for internal graphics", + .default_value = IGD_SM_60MB, + .values = (const struct sm_enum_value[]) { + { " 32 MB", IGD_SM_32MB }, + { " 60 MB", IGD_SM_60MB }, + { " 64 MB", IGD_SM_64MB }, + { " 96 MB", IGD_SM_96MB }, + { "128 MB", IGD_SM_128MB }, + { "160 MB", IGD_SM_160MB }, + SM_ENUM_VALUE_END }, +}); + +/* Legacy 8254 Timer */ +static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({ + .opt_name = "legacy_8254_timer", + .ui_name = "Legacy 8254 Timer", + .ui_helptext = "Enable the legacy 8254 timer by disabling clock gating.", + .default_value = 0, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* S0ix Enable */ +static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({ + .opt_name = "s0ix_enable", + .ui_name = "Modern Standby (S0ix)", + .ui_helptext = "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +/* VT-d */ +static const struct sm_object vtd = SM_DECLARE_ENUM({ + .opt_name = "vtd", + .ui_name = "VT-d", + .ui_helptext = "Enable or disable Intel VT-d (virtualization)", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + +#endif /* _TIGERLAKE_CFR_H_ */ diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 5ebd46dd75dc..82c4c64ff9ef 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -29,7 +29,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); - /* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */ + if (m_cfg->InternalGfx) { + /* IGD is enabled, set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB); + m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB); + } else { + /* IGD is disabled, skip IGD init in FSP. */ + m_cfg->IgdDvmt50PreAlloc = 0; + } + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; @@ -156,7 +164,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->VtdDisable = 1; } else { /* Enable VT-d support for QS platform */ - m_cfg->VtdDisable = 0; + m_cfg->VtdDisable = !get_uint_option("vtd", 1); m_cfg->VtdIopEnable = 0x1; if (m_cfg->InternalGfx) { |