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* 3rdparty/libhwbase: Uprev to avoid new GCC 13 warningNico Huber2023-08-021-0/+0
| | | | | | | | | | | | This pulls just one commit: * commit 584629b9f477 (Avoid warning '"Pos64" is already use-visible') Change-Id: I816f915d991d3d436d0468ca411037b1dc6d0e56 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76867 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* Update libhwbase submodule to upstream masterStefan Reinauer2023-07-051-0/+0
| | | | | | | | | | | | | | | | | | Updating from commit id 8be5a82: 2022-10-04 14:01:00 +0000 - (Fix "unnecessary with of ancestor [-gnatwr]") to commit id 95ad8c5: 2022-12-22 15:32:38 +0000 - (hw-debug: Place global variables in the .bss section) This brings in 1 new commits: 95ad8c5 hw-debug: Place global variables in the .bss section Change-Id: Ib28dbcdf14f313cbfeab03e98e05fffe16a1b708 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75794 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* 3rdparty/libhwbase: Update submodule pointer to 8be5a82b85ceFelix Singer2022-11-261-0/+0
| | | | | | | | Change-Id: I5ad61c39125b19922ae2fdda9767544d857139d0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* 3rdparty/libhwbase: Update to latest ToTPatrick Georgi2021-06-151-0/+0
| | | | | | | | | | This update adds a commit to fix building libgfxinit with gcc 11 Change-Id: I5c0e3823ab7219667f9430bce74e4f2fba0c0c3a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* 3rdparty/libhwbase: Update submodule pointerAngel Pons2020-07-201-0/+0
| | | | | | | | | | | | | | | This brings in 5 new commits: * 69e9086 mutime: Make Sinfo an imported constant * 9f87a10 time: Add T_First constant * 4e22910 Makefile: Adapt $(space) definition * d822df5 Makefile: Delay expansion of `$(ADAFLAGS)` * a3edc6e Makefile: Add `-gnatw_R` to suppress spurious warning Change-Id: I907e66fcf85da256a112a7069a3c551a6d8caaf0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43558 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/libhwbase: Update to current masterNico Huber2019-05-121-0/+0
| | | | | | | | | | | | | | Beside some refactorings that don't affect coreboot, this contains bd0ed91 (Makefile: Revise support for generated sources) that fixes an issue with upcoming libgfxinit configuration changes. Change-Id: Ib47aeff8f6426ae27ddbc235a954e3bd60029072 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32735 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/libhwbase: Update submodule pointerNico Huber2018-05-221-0/+0
| | | | | | | | | | Pull a minor update for GCC 8 compatibility. Change-Id: I0a4af47d56f3ca0b8ed82533e84c44041661ca35 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26306 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber2017-10-281-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplifies our C interface function gma_gfxinit(), due to the following changes: * *libgfxinit* knows about the underlying PCI device now and can probe MMIO addresses by itself. * The framebuffer mapping is now completely handled inside the library where we validate that we neither overflow - the stolen memory, - the GTT address space, the GTT itself nor - the aperture window (i.e. resource2 of the PCI device) that we use to access the framebuffer. Other changes: * Fixes and a quirk for DP training. * Fix for DP-VGA adapters that report an analog display in EDID. * Fixes for Skylake support with coreboot. * DDI Buffer drive-strength configuration for Haswell, Broadwell and Skylake. * `gfx_test` can now be run from X windows (with glitches). * Compatibility with GCC 7 and SPARK GPL 2017. TEST=Booted lenovo/t420 and verified that everything works as usual. Change-Id: I001ba973d864811503410579fd7ad55ab8612759 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* 3rdparty/libhwbase: Update submodule pointerNico Huber2017-06-081-0/+0
| | | | | | | | | | | | | | | Update libhwbase to the current master. Some noteworthy changes: * Add prerequisites for upcoming Apollo Lake support in libgfxinit. * Add some support for Linux user-space for libgfxinit's `gfx_test`. * Fix compilation with GCC 7. Change-Id: If3c65065ef9a2ff6fce221939fda43c9e30c1eb8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Hook up libhwbase in ramstageNico Huber2016-11-291-0/+0
| | | | | | | | | | | | | | | | It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`. This also adds some glue code to use the coreboot console for debug output and our monotonic timer framework as timer backend. v2: Also update 3rdparty/libhwbase to the latest master commit. Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Set up 3rdparty/libhwbaseNico Huber2016-10-291-0/+0
| | | | | | | | | | | | `libhwbase` is a SPARK library that contains some basic support for i/o access, debugging, timers. Just what I put around `libgfxinit`, to make it build standalone. Change-Id: I1918680c14696215522e1c5dae072235bb4e71a3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16948 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* 3rdparty: Move to blobsPatrick Georgi2015-05-051-0/+0
| | | | | | | | | | | | | To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* 3rdparty: move checkout marker forwardStefan Reinauer2015-04-141-0/+0
| | | | | | | | | | Move the 3rdparty marker to blobs.git commit 892a697 Change-Id: I8a51f301e08e49970b4747f004e0752617de8005 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9625 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
* 3rdparty: Update submodule to get Tegra 132 binariesMarc Jones2015-03-071-0/+0
| | | | | | | | | Change-Id: Ib5c967708e1f10e78a752ba28c02271f007fd137 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8613 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* 3rdparty: Update to latest commit (for Intel microcode)Alexandru Gagniuc2015-02-271-0/+0
| | | | | | | | | | | | This pulls in the Intel microcode from blobs, and allows us to move forward with relocating microcode updates in blobs. Change-Id: Iaa046cc20c7825aac168a6ed97c87be548634df3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8356 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* 3rdparty: Update to latest commit in blobs repositoryDave Frodin2015-01-161-0/+0
| | | | | | | | | | 'blobs' now contains the update for the BaldEagle binaryPI. Change-Id: I7ed423b17cee926205792223d6355277bedad552 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* 3rdparty: Update to latest commit in blobs repositoryDave Frodin2015-01-151-0/+0
| | | | | | | | | | | 'blobs' now contains the update for the Mullins binaryPI. Change-Id: Ife5dc73a856697c23a6d6b27fd5280f972992631 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8230 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
* 3rdparty: Update to latest commit in blobs repositoryPaul Menzel2014-12-281-0/+0
| | | | | | | | | | | | | | | | | | Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error occurs) unintentionally reverted commit 16472743 (3dparty: Update to latest commit in blobs repository). Apply that commit again: 'blobs' now contains updates which allow binary AGESA to build with Clang. Pull those in, in anticipation of re-enabling -Werror on Clang builds. Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7963 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* nyan*: I2C: Implement bus clear when 'ARB_LOST' error occursTom Warren2014-12-261-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a fix for the 'Lost arb' we're seeing on Nyan* during reboot stress testing. It occurs when we are slamming the default PMIC registers with pmic_write_reg(). Currently, I've only captured this a few times, and the bus clear seemed to work, as the PMIC writes continued (where they'd hang the system before bus clear) for a couple of regs, then it hangs hard, no messages, no 2nd lost arb, etc. So I've added code to the PMIC write function that will reset the SoC if any I2C error occurs. That seems to recover OK, i.e. on the next reboot the PMIC writes all go thru, boot is OK, kernel loads, etc. BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Tested on nyan. Built for nyan and nyan_big. Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197732 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> (cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc Reviewed-on: http://review.coreboot.org/7897 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
* 3dparty: Update to latest commit in blobs repositoryAlexandru Gagniuc2014-12-221-0/+0
| | | | | | | | | | | | 'blobs' now contains updates which allow binary AGESA to build with clang. Pull those in, in anticipation of re-enabling -Werror on clang builds. Change-Id: I734de0b93ebc1e78781f1d5f48e280badc3cf8b3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7884 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* 3rdparty: Update to latest commit in blobs repositoryPaul Menzel2014-12-011-0/+0
| | | | | | | | | | | | Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support binary AGESA release), which is the latest commit in the blobs repository. Change-Id: I3d643f7565700272c22b59ed764c3269801f4413 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7595 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* blobs: Update to IPQ blob commitMarc Jones2014-11-111-0/+0
| | | | | | | | | | | | | | | | | | | Update the 3rdparty repo to the IPQ binary commit This got updated in error by commit:39bbc8cb97e2de2423cc31bee014ef56884d9f3c Original-Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: http://review.coreboot.org/7354 Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> (cherry picked from commit cfa06c746023fbb79169260012539253811525aa) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibfa243d057f9a2d27e9e02e3e8d4fc6e1da61df0 Reviewed-on: http://review.coreboot.org/7437 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
* Kconfig: Hide DYNAMIC_CBMEM.Vladimir Serbinenko2014-11-091-0/+0
| | | | | | | | | | | Only one setting actually works (exact value depends on board). So no need to show it. Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7359 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
* blobs: Update to IPQ blob commitMarc Jones2014-11-081-0/+0
| | | | | | | | | Update the 3rdparty repo to the IPQ binary commit Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7354 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* AMD Steppe Eagle: Update reference to BLOBs repo (3rdparty)Bruce Griffith2014-09-011-0/+0
| | | | | | | | | | | | | | The BLOBs repo has been updated with AMD PI header files, peripheral BLOBs for the new Avalon southbridge, the AGESA binary PI BLOB for Steppe Eagle, the Steppe Eagle video BIOS, and platform security processor firmware. Change-Id: I8bb58a5cc572d2d75de33b14843d7d1893fff532 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* acpigen: Add acpigen_emit_eisaid.Vladimir Serbinenko2014-06-011-0/+0
| | | | | | | | Change-Id: Ib92142a133445018cd152dabe299792ba5f36548 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5240 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* 3rdparty: update to current HEADPatrick Georgi2014-01-111-0/+0
| | | | | | | | | | It includes a sandybridge fix. Change-Id: I84ff1ac1622b10a4a4aa42517bac0c024c386998 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4642 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* AMD Yangtze: Update 3rdparty hash for new blobsBruce Griffith2013-07-181-0/+0
| | | | | | | | Change-Id: I87de13a7284bc38ac7cf2b18a147323c84a9a5c5 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3780 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Update 3rdparty hash for latest ARM BL1 binariesStefan Reinauer2013-07-101-0/+0
| | | | | | | | | Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3740 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
* Update 3rdparty mark to latest repositoryStefan Reinauer2013-06-281-0/+0
| | | | | | | | | | For new systemagent v6 binaries. Change-Id: I550533fd19c7c5592f3e3c9b514efe2750619c8f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3567 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Update 3rdparty mark to latest repositoryStefan Reinauer2013-03-151-0/+0
| | | | | | | | | | | | | For google/stout binaries Apparently the actual marker got lost in the rebase / change of the commit message. Change-Id: I4f18b9ddba326988b58f2595c0025a113feb0d68 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Eagleheights DSDT: Grant OS control through OSCMike Loptien2013-03-131-0/+0
| | | | | | | | | | | | | | | | | | | | | | Change the OSC method to actually grant control of PCIe capabilities to the OS instead of granting no control. I believe the logic was backwards in the original commit. Bits should be set when granting control and cleared when not granting control. By setting the return value to 0x00, we effectively tell the OS that it cannot control any PCIe capability. See section 6.2.9 of the ACPI spec version 3.0 for more information. This edit is a duplication of the OSC method that is in the src/southbridge/intel/bd82x6x/pch.asl file. Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2714 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Update 3rdparty mark to latest repositoryStefan Reinauer2013-03-131-0/+0
| | | | | | | | | | For google/stout binaries Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2635 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Update 3rdparty mark to latest repositoryStefan Reinauer2013-02-221-0/+0
| | | | | | | | Change-Id: Ied5515a332e3f2f9abbed1c015cad76f7bb4cd9f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2480 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
* Update 3rdparty mark to latest repositoryStefan Reinauer2013-02-111-0/+0
| | | | | | | | Change-Id: Iad3ee8eae9c3551a4078bd48c3f187e694ba6837 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2358 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Update 3rdparty mark to latest repositoryStefan Reinauer2013-01-051-0/+0
| | | | | | | | Change-Id: I59fca4427345c7e677138b944613a1554d5a8331 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2110 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
* Update 3rdparty to it's HEADStefan Reinauer2012-12-121-0/+0
| | | | | | | | Change-Id: I51137bfb3a25e24028b8a05a39339cc67c784980 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2025 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Use new system agent binariesStefan Reinauer2012-11-171-0/+0
| | | | | | | | Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1879 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Updated submodule referenceStefan Reinauer2012-11-121-0/+0
| | | | | | | | | Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ibe0e295293aa0f771063f9c0d1d1e6b69f60007a Reviewed-on: http://review.coreboot.org/1816 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Finally update 3rdpartyPatrick Georgi2012-07-191-0/+0
| | | | | | | | Change-Id: Ic85c1411cd8ccb6b3b96459738fbf8d7d9a2ca77 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1242 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
* Add 3rdparty as submodulePatrick Georgi2012-05-011-0/+0
The build system will make sure only to fetch this if desired by the user. Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/956 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-05 20:30:48 +0000