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* mb/google/nissa/var/gothrax: Adjust touchscreen driverYunlong Jia2023-07-311-12/+14
| | | | | | | | | | | | | | | | Vendor changes touchscreen firmware to use hid method instead of i2c. BUG=b:274707912 BRANCH=None TEST=emerge-nissa coreboot Change-Id: I8e9e0b757e337db6af3fbf3cd4fdbc0079646179 Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76680 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/intel/common/block/pcr: Remove useless break after a returnElyes Haouas2023-07-311-1/+0
| | | | | | | | Change-Id: Ie7f2144d0af21ba111464dfd135159704a3d82b7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76474 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/{auron,link,slippy}/acpi: Drop EC serial portMatt DeVillier2023-07-313-3/+0
| | | | | | | | | | | | | | | | | | | The EC serial port on these devices is not accessible to the end user and exposing it to the OS via ACPI serves no purpose. Debugging over the EC serial port (via the servo interface) does not require the ACPI exist. Drop it since it's not needed and serves no purpose. TEST=build/boot Win11 on auron/link/slippy, verify Windows Device Manager no longer shows an unusable COM port. Change-Id: If453bfca8e094aa06043293bdf91a40c38cc7866 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76793 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/releases/coreboot-4.21: Update toolchain sectionElyes Haouas2023-07-311-3/+4
| | | | | | | | Change-Id: Ie153212a6efa98d7a8942097a1d263837510074d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/alderlake/hsphy.c: Use C99 flexible arraysElyes Haouas2023-07-311-2/+2
| | | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Id0baf970dbe94a8ebf75f8dbabc6abe345d1c454 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* drivers/intel/fsp2_0/fsp_timestamp.c: Use C99 flexible arraysElyes Haouas2023-07-311-1/+1
| | | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I03c21e180e9e399e5cb451bf3b9cfb6484cab68b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76778 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/bsd/cbfs_serialized.h: Use C99 flexible arraysElyes Haouas2023-07-311-3/+3
| | | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I00807a435a21e078c89f797cfd0b00d03604ea0e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76786 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update arm-trusted-firmware submodule to upstream masterElyes Haouas2023-07-301-0/+0
| | | | | | | | | | | | | | | | Updating from commit id c161772f4: 2023-06-08 15:47:09 +0200 - (Merge "refactor(el3-spmc): add emad_advance()" into integration) to commit id 37366af8d: 2023-07-28 17:04:54 +0200 - (Merge "fix(cpus): fix minor issue seen with a9 cpu" into integration) This brings in 287 new commits. Change-Id: Ic364a54154a7b4c5757f9d8abafe2047159ea3ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/amd/common/data_fabric/domain: skip reserved resources for ACPIFelix Held2023-07-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The non-PCI resources added to the domain device are resource consumers, so they mustn't be reported as resource producers. To make sure that this is the case, skip all resources that have the IORESOURCE_RESERVE flag set in amd_pci_domain_fill_ssdt. Commit 7a5dd781d147 ("soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt") that introduced amd_pci_domain_fill_ssdt already contained the bug, but since no MMIO range consumers were added back then, the bug only became visible when commit 32169720bb67 ("soc/amd/common/data_fabric/domain: report non-PCI MMIO resources") added the reserved non-PCI MMIO resources to the domain device's resources resulting in MMIO producer objects being generated for MMIO consumers. Those producers that should have been consumers then overlapped with the actual MMIO resource producers which caused Windows to BSOD with an ACPI_BIOS_ERROR. TEST=The non-PCI MMIO resources are no longer added as resource producers and Windows boots again on google/frostflow. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: Ib099675bc5bea93bf7c2a80f741bef067fd37a58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/amd/common/data_fabric/domain: continue after unassigned resourceFelix Held2023-07-301-1/+1
| | | | | | | | | | | | | When iterating over the resource list in amd_pci_domain_fill_ssdt, don't return when a resource is unassigned, but just continue to the next loop iteration so the resulting SSDT will be complete and not broken due to a missing resource template footer and the scope not being closed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I39fe516f27a6d971fb9c57a1e64ead79d23aff08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* drivers/intel/gma/intel_bios.h: Use C99 flexible arraysElyes Haouas2023-07-301-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I80b4b2df4a38dcbb28d928018446e91acae90ee6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* lib/cbmem_console.c: Use C99 flexible arraysElyes Haouas2023-07-301-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I3d716b29d8e28584a0c9e4056d4c93dca2873114 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76780 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/lynxpoint/me: Use C99 flexible arraysElyes Haouas2023-07-302-2/+2
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: If31cbc5ae184c4eb66011666c1bb655fa16afba0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* include/commonlib/bsd/mem_chip_info.h: Use C99 flexible arraysElyes Haouas2023-07-301-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Ia1d597c0e3e86db8c13829e58a8a27d9de1480b4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76788 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/fsp_relocate.c: Use C99 flexible arraysElyes Haouas2023-07-301-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I52b5a83e7e484889bfef5a4e45a0279fadd58890 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* commonlib/coreboot_tables.h: Use C99 flexible arraysElyes Haouas2023-07-301-7/+7
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I495605190b2c6cd11c7f78727ab4611e10b4d9d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* include/imd_private.h: Use C99 flexible arraysElyes Haouas2023-07-301-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I53ffa4b35d35d4f8b0170377041b258d4bd2eeeb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76777 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/broadwell/pch/me.c: Use C99 flexible arraysElyes Haouas2023-07-301-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Iea63e7ce165b1c8129725136e39bff45765023e6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* include/sar.h: Use C99 flexible arraysElyes Haouas2023-07-301-4/+4
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I688bef264ff41b2a9755133698880fa397f652d4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76755 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/commonn/block/include/psp_efs.h: Remove unused functionFred Reitberger2023-07-281-1/+0
| | | | | | | | | | | | | | | | Commit 49d8aa7043ea ("soc/amd/common/block/psp: Unmap EFS region after use") removed the 'efs_is_valid' function but left the function signature in the header file. TEST=stoney/picasso/cezanne/mendocino/phoenix builds Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib596946679b50be63868af57e3428b4d65845419 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76750 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/nissa/var/gothrax: Tune SX9324 P-sensor configurationYunlong Jia2023-07-282-9/+6
| | | | | | | | | | | | | | | | | | | | Update SX9324 register settings based on tuning value from SEMTECH. －　Enable GPP_B5/GPP_B6 －　Enable GPP_H19 open irq －　Adjust register reg_afe_ctrl0/reg_afe_ctrl3/reg_afe_ctrl4 BUG=b:292016304 BRANCH=None TEST=Check register settings and confirm P-sensor function can work. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I6f15f7a7c428aee45d35830574ef84aefcae6401 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76711 Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* lib: Introduce new parsing rules for ux_locales.cHsuan Ting Chen2023-07-281-34/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce new parsing rules for ux_locales.c:ux_locales_get_text(): * Add a version byte: PRERAM_LOCALES_VERSION_BYTE in the beginning. This provides more flexibility if we want to change the format of preram_locales region. * Add a new delimiter 0x01 between two string_names. This could fix the issue that 'string_name' and 'localized_string' might be the same. Also fix two bugs: 1. We would search for the language ID exceeding the range of current string_name. 2. In 'move_next()', we would exceed the 'size' due to the unconditional increase of offset. Finally, make some minor improvements to some existing comments. BUG=b:264666392, b:289995591 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ic0916a0badd7071fa2c43ee9cfc76ca5e79dbf8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/brask/var/constitution: Add wifi sar tableMorris Hsu2023-07-283-0/+10
| | | | | | | | | | | | | | | | Add wifi sar table for constitution BUG=b:291859402 BRANCH=firmware-brya-14505.B TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I8f99c5cf486cb3e1f2825bbe3a8084f2fe57a41a Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76674 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
* mb/starlabs/starbook: Adjust TCC Offset for all boardsSean Rhodes2023-07-282-6/+6
| | | | | | | | | | | Lower the TCC Offset by 10 degress. Change-Id: Ib80d3b73c41ec1196d8294c35b43333e0df218d5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76374 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/link: Change HDA verb subsystem IDMatt DeVillier2023-07-281-3/+3
| | | | | | | | | | | | | | | | | Change the SSID to allow the correct Creative Labs Windows audio drivers to attach (vs generic HDA audio ones) and provide full functionality. Linux doesn't care about the SSID, so changing it has no effect there. TEST=build/boot Windows, Linux on google/link, verify the correct audio drivers attach under Windows, no regressions under Linux. Change-Id: Ib5e523b07583289b0222ef156245fb0771ad1f1c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76745 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/amd/noncar/memlayout_x86.ld: Conditionally add fspm regionFelix Held2023-07-271-0/+4
| | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e75f29a52179b72b25092f0ffdfd91a182d6648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/amd/noncar/memlayout_x86.ld: Move ramstage link addressArthur Heymans2023-07-271-1/+1
| | | | | | | | | | This address is more certain to not collide with other symbols. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I02eddf43a00c443a1193d6db77d6fad3715216f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/amd/noncar/memmap.c: Support non-FSP use casesFelix Held2023-07-271-1/+6
| | | | | | | | | | | | | Without FSP we assume TSEG is right above CBMEM. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8700803617c3fe4890e497c6d7b94f1d36e21cb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76472 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/noncar/memmap.c: factor out FSP-specific SMM region codeFelix Held2023-07-274-20/+36
| | | | | | | | | | | | | | | Factor out the common FSP-specific code to get the location and size of the SMM region from the HOB that FSP has put into memory. This moves FSP-specific code out of the common AMD SoC code into the FSP-specific common AMD SoC code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie137bb0f4e7438a1694810ae71592a34f9d8c86e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76760 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/common/fsp: factor out read_fsp_resources from root_complex.cFelix Held2023-07-278-114/+43
| | | | | | | | | | | | | | | | Factor out the common FSP-specific code to report the usable and reserved memory resources read from the HOBs that FSP has put into memory. This both reduces code duplication and also moves FSP-specific code out of the SoC code into the FSP-specific common AMD SoC code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib373c52030209235559c9cd383f48ee1b3f8f79b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76759 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/amd/cpu.c: Conditionally define .acpi_fill_ssdtFelix Held2023-07-271-0/+2
| | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I0e81c08191f3c5f768bd3cad0e4915d4476c739f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/nissa/var/uldren: Modify GPIOs for non-touchscreenDtrain Hsu2023-07-271-0/+4
| | | | | | | | | | | | | | | Set GPP_C6(TCHSCR_REPORT_EN) and GPP_C7(TCHSCR_INT_ODL) to NC for non-touchscreen sku. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=build and boot to ChromeOS Change-Id: Ie062eef24f640c3d6c4a0b4c77792e57ac3a722c Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/nissa/var/uldren: Add FW_CONFIG probe for fivrDtrain Hsu2023-07-272-15/+27
| | | | | | | | | | | | | | | | | | Uldren will support internal fivr in next phase and using fw_config to decide the board with internal or external fivr. BUG=b:287379760 BRANCH=firmware-nissa-15217.B TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS work normally. Change-Id: I8a1ac60f599f2895654946d9fa1c4e1f2657fd10 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
* mb/google/nissa/var/craaskov: Add memory parts supportRex Chou2023-07-273-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) LP5 Memory - 2GB Micron MT62F512M32D2DR-031 WT:B 2) LP5 Memory - 2GB Hynix H9JCNNNBK3MLYR-N6E 3) LP5 Memory - 4GB Samsung K3LKBKB0BM-MGCP 4) LP5 Memory - 4GB Hynix H9JCNNNCP3MLYR-N6E DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 1 (0001) H9JCNNNCP3MLYR-N6E 2 (0010) BUG=b:292461498 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I02e49d60e43c4fed8356556ec194d726c30cd609 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/brya/var/anahera: Disable PCH USB2 phy power gatingWisley Chen2023-07-261-0/+5
| | | | | | | | | | | | | | The patch disables PCH USB2 Phy power gating to fix display flicker BUG=b:292403156 TEST=Verified on the defeat board Change-Id: If0c0e655c5d32f39b90635bb3c1d13d8b6993b59 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/trembyle: Update Touchscreen GPIOJon Murphy2023-07-261-1/+1
| | | | | | | | | | | | | | | | | | | Update Touchscreen GPIO to use the correct GPIO 90. GPIO 32 was a copy/paste from dalboz and corresponds to the FP PWR EN on trembyle platforms. BUG=b:292656388 TEST=build/boot morphius Change-Id: Ia6cdbe9195535093e68dbafedaddb70aaf73da88 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76747 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/brya: fix MRC cache failure for hynix partsNick Vaccaro2023-07-261-0/+75
| | | | | | | | | | | | | | | | | | Set the cs_pi_start_high_in_ect if the DUT is using one of the two following Hynix parts: H54G56CYRBX247 and H54G46CYRBX267. Failure to set cs_pi_start_high_in_ect when using these parts will result in an MRC cache failure and DUT will fail to boot. BUG=b:292153199 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot brya variant to kernel. Change-Id: I36040139b959c85c3ac220a34574caa12ca6c5fe Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/myst: Override PSP_SOFTFUSE_BITS to fix non-serial bootKonrad Adamczyk2023-07-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | With currently set default PSP_SOFTFUSE_BITS for phoenix SoC, the non-serial build does not boot on Myst. Override PSP_SOFTFUSE_BITS by disabling SPIConfig to also get the non-serial build booting. The documentation of PSP_SOFTFUSE_BITS is available in #55758 doc (NDA). BUG=b:292489356 TEST=Flash image-myst.bin, verify that it's able to boot on Myst proto0. Change-Id: Id4472fd85fdefcafb8378199dbaa054fab8b3274 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76713 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* mb/samsung/lumpy: override SMBus subsystem IDMatt DeVillier2023-07-261-1/+3
| | | | | | | | | | | | | | | | | Necessary to allow coolstar's Windows touchpad driver for this board, since the touchpad is attached to the SMBus. The VID/DID combo used is not registered/doesn't conflict with any currently in use, and would be difficult to change at this point since the Windows drivers have already been signed. TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify touchpad driver works properly. Change-Id: Ica3756e117fc58166958f37e7b007abb79d9d350 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76744 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/parrot: override SMBus subsystem IDMatt DeVillier2023-07-261-1/+3
| | | | | | | | | | | | | | | | | Necessary to allow coolstar's Windows touchpad driver for this board, since the touchpad is attached to the SMBus. The VID/DID combo used is not registered/doesn't conflict with any currently in use, and would be difficult to change at this point since the Windows drivers have already been signed. TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify touchpad driver works properly. Change-Id: Ie1d882cac90211541a636d2dab297c343a12d66d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76743 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/butterfly: override SMBus subsystem IDMatt DeVillier2023-07-261-1/+3
| | | | | | | | | | | | | | | | | Necessary to allow coolstar's Windows touchpad driver for this board, since the touchpad is attached to the SMBus. The VID/DID combo used is not registered/doesn't conflict with any currently in use, and would be difficult to change at this point since the Windows drivers have already been signed. TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify touchpad driver works properly. Change-Id: I61912fd6db9eb4b8d202ab633b8c7ca5913e759f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/redrix: Disable PCH USB2 phy power gatingWisley Chen2023-07-261-0/+5
| | | | | | | | | | | | | | | The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for redrix board. Please refer Intel doc#723158 for more information. BUG=b:292435264 TEST=build and boot redrix Change-Id: I34d10c763f4710d2c5678704320fd1cc8d8b6287 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76670 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/yavilla: avoid mipi camera LED blinking during launchRobert Chen2023-07-261-3/+1
| | | | | | | | | | | | | | | | | | | Camera LED will blink several times as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:292173903 TEST=Build and boot on Yavilly EVT unit. Verify & observe Camera LED blinking behavior. Change-Id: Ic3e3439dc9313325189761b277e1a3bd1c1d9418 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76671 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/*/root_complex: introduce and use SMN_IOHC_MISC_BASE_13B1Felix Held2023-07-256-5/+7
| | | | | | | | | | | | | | | | On the mobile SoCs, SMN_IOHC_MISC_BASE_13B1 is the only IOHC misc base address, but on for example Genoa it's the address of the IOHC misc base of the second IOHC. Due to it not being the first one on Genoa, use 13B1 as part of the name instead of using an index of 0 which would look odd in the Genoa case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1db28ec03a3ba1c2040d8a1500ae17aa9705f6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76756 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* payloads/external/Linuxboot/Makefile: Guard linux MakefileMaximilian Brune2023-07-251-0/+2
| | | | | | | | | | | The linux.mk makefile needs to be guarded, because it introduces a dependency on the perl tooling. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ieb7aac672072858e0d6811628887f6a9eb9a8cb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* mb/system76/adl: gaze17,oryp10: Remove RTD3 configsTim Crawford2023-07-253-67/+0
| | | | | | | | | | | | These boards do not actually support RTD3. The power GPIOs for components are connected to 3.3V and the reset GPIO is connected to `PLT_RST#`. Change-Id: Id5e318c388f669d6b2935dc98ae29485955e6e72 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/system76/adl: darp8,lemp11: Disable RTD3 on SATA portTim Crawford2023-07-252-12/+14
| | | | | | | | | | | | | | | | | | After switching to S3, it was found that drives on the SATA port do not exit D3cold on S3 exit. Disable RTD3 on the port until the issue can be resolved. Avoids the following error in Linux: pcieport 0000:00:1d.0: Unable to change power state from D3cold to D0, device inaccessible Tested on darp8 with a Samsung 970 EVO or Crucial P5 in J_SSD1. Change-Id: Ib26f59db61acfbf9248cea379c197765d3d9c470 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76593 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/system76/rpl: Add Lemur Pro 12 as a variantJeremy Soller2023-07-2514-0/+501
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Lemur Pro 12 (lemp12) is a Raptor Lake-U board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - DIMM slot with 4800 MT/s memory - Both SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone + mic audio - 3.5mm microphone input - S3 suspend/resume - TPM 2.0 device - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Not working: - Onboard RAM Change-Id: I0c4941534b719ea8fc93eb3492d5fe16db208647 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/system76/rpl: Add Bonobo WS 15 as a variantJeremy Soller2023-07-2512-0/+806
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Bonobo Workstation 15 (bonw15) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots with 5200 MT/s memory - All M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone + mic audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Thunderbolt Change-Id: I6d4e408604a0c5c5272e841f4093baaf28c790cd Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/*/root_complex: don't report root complex IOAPIC resource twiceFelix Held2023-07-255-15/+0
| | | | | | | | | | | | | | | Since the per PCI root IOAPIC is now reported as domain MMIO resource and the IVRS code now again probes for the IOAPIC resource on the domain device, the IOAPIC resource doesn't need to be reported as resource of the northbridge PCI device any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8604bd321ec4239076b1be99dca095e47f8b75a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76600 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 15:10:47 +0000