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* commonlib/coreboot_tables.h: Fix typo in enum type nameAngel Pons2023-04-031-1/+1
| | | | | | | | | | | | | Fix a typo in an enum's type name, "tmp" ---> "tpm". The enum type is not used anywhere in the coreboot tree. Change-Id: Ie7529e7ee80aa9661ec053da8211c2c3295b3942 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* soc/amd/cezanne,glinda,mendocino,phoenix,picasso/Kconfig: use all targetFelix Held2023-04-035-25/+10
| | | | | | | | | | | | | | The i2c.c compilation unit is added to all stages in all cases, so use the all target instead of adding it to all stages separately. Also order the all targets alphabetically. TEST=Timeless build on Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie90380075a3c87d226cdcb0f41f7e94275eaaa42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* mb/amd/birman/port_descriptors: split files for phoenix/glindaFred Reitberger2023-04-033-2/+134
| | | | | | | | | | | Glinda and Phoenix have different requirements, so split the birman port_descriptors file to betty apply to each SoC. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia28cf4172b6adada10809e0135b2459077fa3da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_empMorris Hsu2023-04-031-0/+13
| | | | | | | | | | | | | | | Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX signal integrity issue. BUG=None TEST=build FW and check Type-A USB3 port0/port1 RX pass Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current valuesJeremy Compostella2023-04-031-8/+8
| | | | | | | | | | | | | | | | | | | The Intel Power and Performance (PnP) team requested to update the following: - TDC settings for RPL-U 15W variant should be 22A. - TDC settings for RPL-P 28W variant should be 33A. BUG=b:275694022 BRANCH=firmware-brya-14505.B TEST=PnP validated performance impact with these settings on both RPL-U 15W and RPL-P 28W Change-Id: I1141414785a990b975e32ebc03e490b83082aab7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74046 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/hades: Add CPU power limitsTarun Tuli2023-04-034-0/+68
| | | | | | | | | | | | | | Add CPU power limits support and values for RPL on Hades BUG=b:269371363 TEST=builds Change-Id: I22ef56152abe5a23067c5e923b07d60dc9fac8e7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73895 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/ppc64/rom_media.c: move to mainboard/emulation/qemu-power*Krystian Hebel2023-04-035-3/+19
| | | | | | | | | | CBFS location in memory is different than on the real hardware. Change-Id: Icd806a57f449042c883b624056c05c1ff7e4c17e Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
* util/crossgcc/buildgcc: Allow bootstrapping CMake with multiple threadsFelix Singer2023-04-031-0/+1
| | | | | | | | | | | The main build process already runs multi-threaded, when requested. Apply the same setting to the bootstrap / configure step. Change-Id: I89d6728a0985946b702f83770bedf767afb12690 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74156 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/uldren: Add overridetreeVan Chen2023-04-034-2/+319
| | | | | | | | | | | | | | | | | Add override devicetree based on schematics(ver. 20230308). BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9cd918c6a48cc6007a18c5aa94afe31fd9608718 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73974 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* soc/intel/common: Order the CPUs based on their APIC IDsSridhar Siricilla2023-04-021-57/+64
| | | | | | | | | | | | | | | | | The patch defines acpi_set_cpu_apicid_order() which orders the APIC IDs based on APIC IDs of Performance cores and Efficient cores, calculates the total core count and total Performance cores count, populates the information in the cpu_apicid_order_info struct. The helper function useful to present the Performance and Efficient cores in order to OS through MADT table and _CPC object. TEST=Verify the build for Gimble (Alder Lake board) Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72131 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Set Power Performance Platform OverrideSubrata Banik2023-04-021-1/+2
| | | | | | | | | | | | | | According to document 640858 MTL EDS Vol2, bit 18 (PWR_PERF_PLATFRM_OVR) of MSR_POWER_CTL must be set. This patch is backported from `commit 117770d32468e63df ("soc/intel/ alderlake: Enable Energy/Performance Bias control")`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74155 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Add EPP override supportSubrata Banik2023-04-022-1/+24
| | | | | | | | | | | | | | | | | | This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. This patch is backported from `commit 0bb2225718ef898c ("soc/intel/alderlake: Add EPP override support")`. BUG=b:266522659 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8172276159fe3987dae36ec30ebceb76dd0ef326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74154 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/coreboot_tables.h: Replace spaces with tabsAngel Pons2023-04-021-1/+1
| | | | | | | | | | | | Indent with tabs for the sake of consistency with the rest of the code. Change-Id: Ibd325a7a8348cc1f9023e54dceab40d02a0df233 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph2023-04-0210-12/+13
| | | | | | | | | | | | | | | | | | | Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* crossgcc: Upgrade CMake from version 3.25.2 to 3.26.2Elyes Haouas2023-04-023-2/+2
| | | | | | | | Change-Id: I62078257fd84a64c699a7f930bc306e38d2f4058 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73791 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/crossgcc: Update binutils from 2.37 to 2.40Felix Singer2023-04-016-210/+243
| | | | | | | | Change-Id: I34a20a999f7ea624c1add4750fcd116166953dd8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/google/rex: Add FW_CONFIG for FP/UWB/WIFISubrata Banik2023-04-011-0/+13
| | | | | | | | | | | | | | | | This patch adds FW_CONFIG to accommodate different Rex BoM components across various SKUs. 1. Fingerprint sensor - FP Present/Absent 2. Ultra wideband - UWB Absent/Using BITBANG/Using GSPI1 3. WIFI - CNVi/PCIe TEST=Able to build and boot google/rex. Change-Id: I97b0dc25f239103a0a235f14b50008a633e2f88d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
* mb/google/rex: Update Rex Flash LayoutSubrata Banik2023-04-012-39/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the Rex flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. For default chromeos.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. For chromeos-debug-fsp.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.2MB. RW_LEGACY: Dropped RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections BUG=b:262868089 TEST=Able to enable CSE update on google/rex and have free space to add one more PUNIT FW for support different SoC stepping. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/amd/stoneyridge: factor out P-state utils to link in all stagesFelix Held2023-04-013-54/+64
| | | | | | | | | | | | | | | | | tsc_freq.c gets built into all stages, but the tsc_freq_mhz function it implements calls the get_pstate_0_reg function which was only built into ramstage. Since tsc_freq_mhz was only called in ramstage, commit 2323acab6a7a ("soc/amd/stoneyridge: implement and use get_pstate_0_reg") didn't cause the build to fail, but better factor out the P-state- related utility functions into a separate compilation unit and include it in all stages that also include tsc_freq.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3a3ee218f495be5e60a888944487704e7e8a1a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/stoneyridge/Makefile: use all target for more compilation unitsFelix Held2023-04-011-15/+3
| | | | | | | | | | | | | | | monotonic_timer.c, tsc_freq.c and uart.c get added to all stage targets, so just add those to the all stage targets. They still need to be added to the smm stage target, since the all target doesn't add things to the smm stage. TEST=Timeless build results in identical image for Gardenia. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I16c02bc0ff54553f212b94d110abef6a7bdedbb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74144 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/docker/coreboot-sdk: Remove Python 2 packageFelix Singer2023-04-011-2/+1
| | | | | | | | | | | | | Debian removed Python 2 from their Sid repository and so it needs to be removed from the Dockerfile as well. Built and tested the Dockerfile with Python 2 removed. Still works. Change-Id: If4e298dc275c1dfaf57cd4c3f8e5f89410318ec0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/intel/xeon_sp/spr: Add ACPI support for Sapphire RapidsJonathan Zhang2023-04-0113-48/+2411
| | | | | | | | | | | | | | | | Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests. The code was written from scratch because there are Xeon-SP specific implementation especially Integrated Input/Output (IIO). Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967 Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/google/rex: Add fmd for debug FSPSubrata Banik2023-04-012-0/+59
| | | | | | | | | | | | | | | | | | | | | Debug FSP is ~920KiB larger than release FSP and we don't have sufficient space for rex flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. Note: This fmd will only used for internal testing/debugging and not for the firmware in released devices. BUG=b:262868089 TEST=Build google/rex with CONFIG_BUILDING_WITH_DEBUG_FSP. Change-Id: I58b0af9c43c5d096dc80084497b39f13f67c25cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/meteorlake: Add BUILDING_WITH_DEBUG_FSPSubrata Banik2023-04-011-0/+6
| | | | | | | | | | | | | | | | | Intel FSP has "debug" build which is not public, used for debugging by approved developers. Add a Kconfig to indicate that coreboot is building with debug version of FSP so we can adjust few things (i.e. flash layout) in the case. BUG=b:262868089 TEST=Able to build and boot google/rex. Change-Id: I5555a2ab4182ad0036c42be6fea3d934ffd0db8c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/meteorlake: Fix PortUsb30Enable configurationIvy Jian2023-04-011-1/+0
| | | | | | | | | | | | | | | PortUsb30Enable has been overridden unexpectedly, this patch fixed it. BUG=b:276181378 Test=boot to rex and check USB3 ports are working. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ic04b9eb236ed28a76ee516c52fc0c983cb8f2c0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/meteorlake: Enable 'struct cpu_info' update for MTLSridhar Siricilla2023-04-011-0/+3
| | | | | | | | | | | | | | The patch enables addition of core_type member to 'struct cpu_info' for MeteorLake platform. TEST=Build and verify the code for Rex Change-Id: I01abed6b87bec2f8eb39bfc941faff070b83abe6 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74130 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/amd/common/block/cpu/tsc/Makefile: order targets by stageFelix Held2023-03-311-14/+5
| | | | | | | | | | | | | Now that only one build target per stage is included in the build depending on CONFIG_SOC_AMD_COMMON_BLOCK_TSC being set, don't use a separate ifeq block for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9e551b37707081eb2ea1d682013f57c7ca8aabd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74017 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/cpu: use TSC_MONOTONIC_TIMER for SOC_AMD_COMMON_BLOCK_TSCFelix Held2023-03-315-33/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All AMD SoCs with Zen-based CPU cores are already using timestamps based on the TSC counter, so use the existing common infrastructure instead of reimplementing it in a similar way. The behavior of the code changes slightly, but results in identical timestamps. The timestamp_get implementation in soc/amd/common/block/cpu divided the result of rdtscll() in timestamp_get by the result of tsc_freq_mhz() and didn't override the weak timestamp_tick_freq_mhz implementation that returns 1. The non AMD specific code returns the result of rdtscll() in timestamp_get, but returns tsc_freq_mhz() instead of 1 in timestamp_tick_freq_mhz, so we still get the correct timestamps. TEST=The raw timestamps printed on the serial console are now multiplied by the expected factor of the TSC frequency in MHz. TEST=Normalized timestamps printed on the serial console by the x86 code don't change significantly on Mandolin when comparing before and after this patch. A slight variation in the timestamps is expected. An example would be: Before: CPU_CLUSTER: 0 init finished in 630 msecs After: CPU_CLUSTER: 0 init finished in 629 msecs TEST=The calculations of the time spent in verstage on PSP before entering the bootblock on Guybrush result in similar times when multiplying the value before the patch with the TSC frequency in the case with the patch applied. The raw values printed on the serial console by the verstage on PSP use the 1us time base, but the timestamp logs that end up in CBMEM will be fixed up to use the same time base as the x86 part of coreboot. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I57b732e5c78222d278d3328b26bb8decb8f4783e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/skyrim: Disable L1.2 for SD portMartin Roth2023-03-311-1/+0
| | | | | | | | | | | | | | | | | | | | | Having L1.2 enabled on the SD port increases the kernel resume times by between 30 & 40ms. This patch disables L1.2 on SD to get that time back. As with needing to have hotplug enabled on the SD card, this seems like a driver issue, so hopefully that will get sorted out and this patch can be reverted. BUG=b:274025743 TEST=resume times are decreased. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2c409fa2cd66c712c5ba7104635499d63fa0d2be Reviewed-on: https://review.coreboot.org/c/coreboot/+/74118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella2023-03-312-1/+2
| | | | | | | | | | | | | | | | | | | | | | Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/cse: Handle EOP completion asynchronouslyJeremy Compostella2023-03-313-35/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot supports three instances of sending EOP: 1. At CSE `.final' device operation 2. Early as with Alder Lake in chip_operations.init if `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected 3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if `SOC_INTEL_CSE_SEND_EOP_LATE' is selected Currently, Alder Lake uses #3 as it results in better and more stable boot time. However, what would deliver even better result is to not actively wait for CSE completion. This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig which split the action of sending EOP request and receiving EOP completion response from the CSE. This patch used in conjunction with #1 can significantly improves the overall boot time on a Raptor Lake design. For example `SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 1 | 1020.052 | 971.272 | | 2 | 1015.911 | 971.821 | | 3 | 1038.415 | 1021.841 | | 4 | 1020.657 | 993.751 | | 5 | 1065.128 | 1020.951 | | 6 | 1037.859 | 1023.326 | | 7 | 1042.010 | 984.412 | |----------+----------+-----------| | Mean | 1034.29 | 998.20 | | Variance | 4.76 % | 5.21 % | The improvement is not stable but comparing coreboot and FSP performance timestamps demonstrate that the slowness is caused by a lower memory frequency (SaGv point) at early boot which is not an issue addressed by this patch. We also observe some improvement on an Alder Lake design. For example, the same configuration on a kano board can deliver up to 10 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 0 | 1067.719 | 1050.106 | | 1 | 1058.263 | 1056.836 | | 2 | 1064.091 | 1056.709 | | 3 | 1068.614 | 1055.042 | | 4 | 1065.749 | 1056.732 | | 5 | 1069.838 | 1057.846 | | 6 | 1066.897 | 1053.548 | | 7 | 1060.850 | 1051.911 | |----------+----------+-----------| | Mean | 1065.25 | 1054.84 | The improvement is more limited on kano because a longer PCIe initialization delays EOP in the Late EOP configuration which make it faster to complete. CSME team confirms that: 1. End-Of-Post is a blocking command in the sense that BIOS is requested to wait for the command completion before loading the OS or second stage bootloader. 2. The BIOS is not required to actively wait for completion of the command and can perform other operations in the meantime as long as they do not involve HECI commands. On Raptor Lake, coreboot does not send any HECI command after End-Of-Post. FSP-s code review did not reveal any HECI command being sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or `END_OF_FIRMWARE' notifications. If any HECI send and receive command has been sent the extra code added in `cse_receive_eop()' should catch it. According to commit 387ec919d9f7 ("soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first boot after flashing of a Marasov board for instance) request coreboot to perform a global request out of AFTER_PCI_ENUM notification. Global request relies on a HECI command. Even though, we tested that it does not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent potential a global reset command to "conflict" with the EOP command. BUG=b:276339544 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post sent soon after FSP-s and EOP message receive at `BS_PAYLOAD_BOOT'. Verify robustness by injecting a `GET_BOOT_STATE' HECI command with or without `heci_reset'. The implementation always successfully completed the EOP before moving to the payload. As expected, the boot time benefit of the asynchronous solution was under some injection scenario undermined by this unexpected HECI command. Change-Id: Ib09dcf9140eb8a00807a09e2af711021df4b416f Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73619 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/amd/picasso/graphics: use RAVEN2_VBIOS_REV with RAVEN2_VBIOS_VID_DIDFelix Held2023-03-311-0/+3
| | | | | | | | | | | | | In order for the code to find the correct VBIOS file in CBFS, remap the revision ID in the RAVEN2_VBIOS_VID_DID case to the one that matches the CBFS file name. This will make the code work as expected on devices with the PCI ID RAVEN2_VBIOS_VID_DID and a revision != RAVEN2_VBIOS_REV. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94412dc2e778e7c4f74e475cd49114a00a81b2ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/74045 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/dq67sw: Add LGA1155 microATX mainboardMichael Büchler2023-03-3119-0/+759
| | | | | | | | | | | | | | | This is a new port for the Intel DQ67SW desktop board. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM. A list of tested working and non-working features is in the documentation page. Change-Id: Ifc703f2d0ad45495e71d3f7799347430f5196791 Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Add Asus P8Z77-MKeith Hui2023-03-311-0/+137
| | | | | | | | Change-Id: I01f990408c4552b69c04e849e7faaf9f51f24a51 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/dedede/var/kracko: Add fw_config probe for ALC5682-VD/ALC5682-VSRobert Chen2023-03-311-1/+25
| | | | | | | | | | | | | | | | | | ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:275644832 TEST=emerge-dedede coreboot BRANCH=firmware-dedede-13606.B Change-Id: I644f3aa3187e08146d78abb70a568833bc9b9211 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/nissa/var/uldren: Update gpio settingsVan Chen2023-03-312-0/+103
| | | | | | | | | | | | | | | | Configure GPIOs according to schematics(ver. 20230308). BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id414c9b0d94faffd2d71c348fc7146a6101196e9 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* mb/google/brya/variants/hades: Add initial GPIO config for hades boardTarun Tuli2023-03-314-53/+489
| | | | | | | | | | | | | | | | | | | Initial hades GPIO config. Combination of original brya basebaord, Agah and new arbitrage output for hades design. Also moved GPIO config to the non baseboard variant model as we did on rex0. BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I2a850240dd7f3ddf137d6a2ebe8a147f8976c16b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/alderlake: Enable 'struct cpu_info' update for ADLSridhar Siricilla2023-03-311-0/+3
| | | | | | | | | | | | | | The patch enables addition of core_type member to 'struct cpu_info' for Alderlake platform. TEST=Build and verify the code for Gimble Change-Id: Ia065b98c2013e78328fd38bed9c667792d6d1f4d Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74089 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/common: Add core_type member to 'struct apic_path'Sridhar Siricilla2023-03-313-0/+16
| | | | | | | | | | | | | | The patch adds new member 'core_type' to the 'struct apic_path' and updates core type information. TEST=Build the code for MTL Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/amd/picasso/graphics: refactor map_oprom_vendev_revFelix Held2023-03-301-11/+10
| | | | | | | | | | | Refactor map_oprom_vendev_rev as a preparation to also remap the revision ID in the RAVEN2_VBIOS_VID_DID case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b81a9464ed49672889fcb767920154fe6efdfcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/amd/birman/early_gpio: Add M2 SSD resetsFred Reitberger2023-03-301-0/+4
| | | | | | | | | | Add early configuration of the GPIOs that control the M2 SSD resets. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I81439d193bdd7296d8a8fea83c5c6be2c75adbea Reviewed-on: https://review.coreboot.org/c/coreboot/+/73989 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/birman/port_descriptors.c: Add USB-C configurationFred Reitberger2023-03-301-4/+4
| | | | | | | | | | | Add option decode for USB-C DDI connection type and remove unnecessary break after return. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If38fa667daeb2dd176ecdf33abaec9b56d633a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Revert "mb/google/rex: Enable VPU"Kapil Porwal2023-03-301-1/+0
| | | | | | | | | | | | | | | | | This reverts commit 555ceca38a78 ("mb/google/rex: Enable VPU"). Reason: Unable to boot to latest OS image with VPU enabled. BUG=none TEST=Boot to OS image 15376 on google/rex Change-Id: If61282528922304373d492b362056b52995cbcad Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/asrock/h77pro4-m: Make onboard NIC a child device below PCIe port 6Kevin Keijzer2023-03-301-0/+1
| | | | | | | | | | | | | | | | | The Realtek RTL8111E NIC is currently not defined as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp4s0 rather than eno0, as is appropriate for on-board ethernet devices. This patch defines the NIC as a child device of PCIe port 6, so that it's properly defined as an on-board device. Change-Id: I2e1b65e4d27852297a739e332c52c15a8c81b858 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74090 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/intel/fsp2_0/hand_off_block: use cb_err in fsp_find_range_hobFelix Held2023-03-303-8/+8
| | | | | | | | | | | | | | | Use enum cb_err as return value of fsp_find_range_hob instead of using the raw -1 and 0 values. Also update the call sites accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6c9f69a886f53868f1ef543c8fa04be95381f53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/common/block/cpu/noncar/memmap: simplify return value checkFelix Held2023-03-301-3/+1
| | | | | | | | | | | | | | | Since the return value of the fsp_find_range_hob call is only used in one location, move the call and return value check into the if condition block to not need the status variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9e9251368b86382dc4e050cf176db79dbfb230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* console: Deselect using ANSI escape characters when SimNow is usedZheng Bao2023-03-301-1/+1
| | | | | | | | | | | To remove the annoying "ESC [1m" at SimNow console window. Change-Id: I300aee946f342f41b94288b75b843956de9d3e88 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/prodrive/atlas: Rework EEPROM layout structuresAngel Pons2023-03-302-32/+26
| | | | | | | | | | | | | | | | | To avoid having to calculate the length of a struct separately, rework the code to give the struct a tag name, so that `sizeof()` can be used instead. This involves refactoring the `get_emi_eeprom_vpd()` function to return a struct instead of a union, so callers can no longer access the EEPROM data as an array of bytes without additional code, but this array view is only used inside `get_emi_eeprom_vpd()` when reading the data from EMI. Change-Id: Id1bc40939631baa131b5f60eadbfe42838294ebe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/alderlake: Avoid reprogramming the SRAM BARSubrata Banik2023-03-301-5/+31
| | | | | | | | | | | | | | | | | | | | | | This patch avoids the redundant programming of SRAM BAR when the SRAM PCI device is enabled. Rather read the PCH SRAM Base Address Register while enabling crashlog feature. Additionally, this patch relies on PCI enumeration to get the SRAM BAR rather than hijacking the SPI temporary base address which might have resulted in problems if SPI is disabled on some platform with BAR being implemented. TEST=Able to build and boot google/marasov and crashlog is working. Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/nissa/var/yavilla: Disable storage devices based on fw_configTony Huang2023-03-303-0/+73
| | | | | | | | | | | | | | | | Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:273791621 TEST=emerge-nissa coreboot Change-Id: I1a6013e0ad0c430d83bbbad4b92392c8c4815b0d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 08:05:58 +0000