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* soc/mediatek/mt8188: Shut down PMIC on power key long pressSen Chu2023-03-151-1/+1
| | | | | | | | | | | | | | | | | | | Currently on power key long press, PMIC will be reset. It would cause an unwanted reset pulse in the power-off sequence. To match expected sequence, change PMIC behavior to "force shutdown". BUG=b:271771606 TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse Change-Id: I1626892fd582dfab8fe1c1ede1da00549bc97142 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73704 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/omnigul: Correct mux_conn for USB C1Dtrain Hsu2023-03-151-1/+1
| | | | | | | | | | | | | | | | | | Modify USB C1 mux_conn to 1. It should match ec settings. BUG=b:272394875, b:272667290 BRANCH=firmware-brya-14505.B TEST=Plug USB-C hub in USB C1 and could recognize USB drive and hdmi. Change-Id: I61b77405d1790b044174cef954e5bf910141f424 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/omnigul:Fixed can't detect 3.5mm headphone jackJamie Chen2023-03-151-1/+1
| | | | | | | | | | | | | | | | 1. Modify irq_gpio GPP_H0 -> GPP_A23 BUG=b:272218750 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I8e178b149015ed8027b547e4c2109b3aef8a7484 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/omnigul:Fixed Touch screen has no actionJamie Chen2023-03-151-0/+2
| | | | | | | | | | | | | | | | 1. Add generic.stop_gpio = GPP_C6 2. Add c.stop_off_delay_ms = 2 BUG=b:271966059 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I33857443d8a68e7b50ac5f8f08afc017fe4f5a59 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim/var/frostflow: Update the STT settingsFrank Wu2023-03-141-8/+8
| | | | | | | | | | | | | | | | | According to file thermal_table_0310, adjust the STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Change-Id: If4500c85dcea051aca15602f1fb4b5ec80b73e67 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
* mb/google/dedede/var/dibbi: Configure I2C times for audioAmanda Huang2023-03-141-1/+6
| | | | | | | | | | | | | | | | Configure the I2C bus high and low time for audio. BUG=b:271804915 BRANCH=dedede TEST=Build and confirm I2C clock for audio is between 380 kHz and 400 kHz Change-Id: I2987a39abc5527844424edfa1cf70d5c5cea5357 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya: Create uldren variantvan_chen2023-03-148-0/+45
| | | | | | | | | | | | | | | | | | | | | | Create the uldren variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:271513530 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ULDREN Change-Id: Ibbcd34fb4ef1f7464f0c94d2fcf75280c3eed6be Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73680 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Enable early caching of TOM regionSubrata Banik2023-03-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Intel Meteor Lake decides to enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_TOM` config. TEST=Able to build and boot google/rex to ChromeOS and reduce the boot time by 77 ms. Without this patch: 950:calling FspMemoryInit 936,811 (19,941) 951:returning from FspMemoryInit 1,041,935 (105,123) With this patch: 950:calling FspMemoryInit 905,108 (20,103) 951:returning from FspMemoryInit 964,038 (59,929) Change-Id: Iebb3485b052386b43d5bccd67a04e6115cbcc20d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73274 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/fsp2_0: Have provision for caching TOM regionSubrata Banik2023-03-131-0/+10
| | | | | | | | | | | | | | This patch enables early caching of TOM region to optimize the boot time if valid mrc cache is found (i.e. except the first boot after flashing/updating few AP firmware image). TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia575ad0f99d5b0fd015e40b0862e8560700f6c83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/cmn/sa: Store TOM into the CMOSSubrata Banik2023-03-132-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the IA common code API to store the top_of_ram (TOM) address intonon-volatile space (CMOS). The code logic will update the TOM address in CMOS NVS if the `top_of_ram` address is calculated differently in any boot and also takes care of caching the updated range. TEST=Able to build and boot google/rex to ChromeOS. First boot: Before calling into FSP-M [DEBUG]  0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB [DEBUG]  0x00003ffffff80800: PHYMASK0: Length  = 0x0000000000080000, Valid [DEBUG]  0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB [DEBUG]  0x00003ffffffc0800: PHYMASK1: Length  = 0x0000000000040000, Valid [DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG]  0x00003fffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid [DEBUG]  0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP [DEBUG]  0x00003fffff800800: PHYMASK3: Length  = 0x0000000000800000, Valid ... [DEBUG] tom_table invalid signature [DEBUG]  top_of_ram = 0x76000000 [DEBUG] Updated the TOM address into CMOS 0x76000000 On consecutive boot:Before calling into FSP-M: The TOM region is already cached. [DEBUG]  0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB [DEBUG]  0x00003ffffff80800: PHYMASK0: Length  = 0x0000000000080000, Valid [DEBUG]  0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB [DEBUG]  0x00003ffffffc0800: PHYMASK1: Length  = 0x0000000000040000, Valid [DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG]  0x00003fffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid [DEBUG]  0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP [DEBUG]  0x00003fffff800800: PHYMASK3: Length  = 0x0000000000800000, Valid [DEBUG]  0x0000000075000005: PHYBASE4: Address = 0x0000000075000000, WP [DEBUG]  0x00003fffff000800: PHYMASK4: Length  = 0x0000000001000000, Valid Change-Id: I2569495570652c488096f6a29f58dd8f0103af9d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73273 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/tom: Cache TOM region earlySubrata Banik2023-03-134-0/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a module that can store the top_of_ram (TOM) address into non-volatile space (CMOS) during the first boot and use it across all consecutive boot. As top_of_ram address is not known until FSP-M has exited, it results into lacking of MTRR programming to cache the 16 MB TOM, hence accessing that range during FSP-M and/or late romstage causing long access times. Purpose of this driver code is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot google/rex to ChromeOS. Without this patch: 950:calling FspMemoryInit               936,811 (19,941)   951:returning from FspMemoryInit        1,041,935 (105,123) With this patch:  950:calling FspMemoryInit               905,108 (20,103)   951:returning from FspMemoryInit        987,038 (81,929) Change-Id: I29d3e1df91c6057280bdf7fb6a4a356db31a408f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73272 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* top/Makefile.inc: Define regions-for-file with a flexibilityZheng Bao2023-03-131-1/+1
| | | | | | | | | | | | | | | If we need to put a CBFS chunk into a specific region, add a line in any Makefile.inc regions-for-file-xxx=region_name TODO:Do a complete binary identical test for all the mainboards. Change-Id: Ie37a8a9230dc8b8e5664be8806f047afb94fba69 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/phoenix/mca.c: Remove excess MCA bank namesFred Reitberger2023-03-131-32/+0
| | | | | | | | | | | | Documentation and hardware differ in the number of MCA bank names, so remove the excess ones to prevent a "CPU has an unexpected number of MCA banks!" warning message. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I75a2348561833f3f19181b4f30a6971ecb317899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block/cpu/update_microcode: use raw MSR dataFelix Held2023-03-131-2/+1
| | | | | | | | | | | | | Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, the address of the microcode update can be directly written to the raw value instead of needing to split it into the lower and higher 32 bits and assigning those separately. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51c84164e81477040a4b7810552d3d65c0e3656b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/common/block/cpu/noncar/write_resume_eip: use raw MSR dataFelix Held2023-03-131-2/+1
| | | | | | | | | | | | | | Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, the address of the bootblock_resume_entry can be directly written to the raw value instead of needing to split it into the lower and higher 32 bits and assigning those separately. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7ebab1784ec592e18c29001b1cf3ee7790615bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* arch/x86/include/arch/mmio.h: Provide __always_inline definition for muslFabian Groffen2023-03-131-0/+4
| | | | | | | | | | | | fix compilation on musl-libc systems by providing an implementation for __always_inline Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I01a7eb9ed28e79523623ab362510ec2d93f4a8b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73667 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Select `X86_CLFLUSH_CAR` configSubrata Banik2023-03-131-0/+1
| | | | | | | | | | | | | | | This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b2dce39f82e28cd99ad8621c78bae494c4f16ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/73333 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cpu/x86/cache: CLFLUSH programs to memory before runningArthur Heymans2023-03-136-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | When cbmem is initialized in romstage and postcar placed in the stage cache + cbmem where it is run, the assumption is made that these are all in UC memory such that calling INVD in postcar is OK. For performance reasons (e.g. postcar decompression) it is desirable to cache cbmem and the stage cache during romstage. Another reason is that AGESA sets up MTRR during romstage to cache all dram, which is currently worked around by using additional MTRR's to make that UC. TESTED on asus/p5ql-em, up/squared on both regular and S3 resume bootpath. Sometimes there are minimal performance improvements when cbmem is cached (few ms). Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37196 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Add Kevin Keijzer for ASRock B75M-ITXKevin Keijzer2023-03-131-0/+5
| | | | | | | | | Change-Id: I6f2047e62c1e999823bf98acaf3530aa62478449 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Fabian Groffen <grobian@gentoo.org>
* mb/google/skyrim/var/winterhold: Change touch controller T3EricKY Cheng2023-03-131-1/+1
| | | | | | | | | | | | | | | | | Change stop_delay_ms time(T3) from 180 to 150 to meet specification. T3 min-value of HID-I2C should be 150ms. BUG=b:267280863 TEST=emerge-skyrim coreboot chromeos-bootimage. Change-Id: I7ef7db4edaecece1fa5ab07e30a80e556ed35f8b Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brask/var/kinox: Allow USB2/3 hotplug to wakeup S0ixDtrain Hsu2023-03-131-0/+11
| | | | | | | | | | | | | | | | Allow USB2/3 hotplug event to wake up S0ix. BUG=b:236189998 BRANCH=firmware-brya-14505.B TEST=Verify USB-A device could wake up Kinox Change-Id: I8aeeeac6c21289b70bdc7ffddc57687ac39e8456 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* util/inteltool: Fix build on musl-libc systemsFabian Groffen2023-03-121-1/+1
| | | | | | | | | | use __linux__ instead of __GLIBC__ guard for Linux-specific includes Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Ifbf4552591c0df7811c5b37a9207c0901b6fd68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73666 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/superiotool: Fix build on musl-libc systemsFabian Groffen2023-03-122-2/+8
| | | | | | | | | | | - use __linux__ instead of __GLIBC__ guard for Linux-specific includes - use POSIX ioperm instead of deprecated iopl Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I99613007aa9feddcb1041f31085cdeb195ff7a68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* top/Makefile.inc: add _tohexZheng Bao2023-03-101-0/+1
| | | | | | | | | | Get string of hex value of a given number. Change-Id: I6d3525db19089938897b9d19ad9875bb07e0eecf Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/common/psp: Put spl_fuse in separate compilation unitMartin Roth2023-03-104-54/+57
| | | | | | | | | | | | | | | | | This separates the SPL fusing function into a separate C file which can be excluded if it is not needed. This allows the psp_set_spl_fuse() function to be made static again as the state of the function will always match the boot_state entry. Move the required #defines to the common header file so they can be used by both psp_gen2.c & spl_fuse.c. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ifbc774a370dd35a5c1e82f271816e8a036745ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73655 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/common/cpu/smm/smm_relocate: don't assume TSEG is below 4GBFelix Held2023-03-101-4/+2
| | | | | | | | | | | | | | | | | | | | Even though right now TSEG will always be located below 4GB, better not make assumptions in the SMM relocation code. Instead of clearing the higher 32 bits and just assigning the TSEG base and per-core SMM base to the lower 32 bits of the MSR, assign those two base addresses to the raw 64 bit MSR value to not truncate the base addresses. Since TSEG will realistically never be larger than 4GB and it needs to be aligned to its power-of-two size, the TSEG mask still only needs to affect the lower half of the corresponding MSR value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1004b5e05a7dba83b76b93b3e7152aef7db58f4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/amd/common/block/psp/psp_smm: use raw MSR dataFelix Held2023-03-101-2/+2
| | | | | | | | | | | | | | | | Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, there's no need to convert the lower and higher 32 bits into a 64 bit value and we can just use the 64 bit raw value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5923df84f0eb3a28ba6eda4a06c7421f4459e560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/amd/stoneyridge/monotonic_timer: use raw MSR dataFelix Held2023-03-101-4/+1
| | | | | | | | | | | | | | | | Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, there's no need to convert the lower and higher 32 bits into a 64 bit value and we can just use the 64 bit raw value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibc5d64c74eaabfc4b7834a34410b48f590f78a12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mp_init: Wait longer for APs to check inPatrick Rudolph2023-03-101-2/+3
| | | | | | | | | | | | | | | On IBM/SBP1 with 384 cores it takes a while for all APs to check in. Use linear scaling instead of hardcoding an arbitrary limit for the timeout. Change-Id: If020a3fa985bfc7fd2f0aa836dc04e6647a1a450 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: TangYiwei Reviewed-by: Naresh <naresh.solanki.2011@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* xeon_sp: Setup x2apic in SRATNaresh Solanki2023-03-101-4/+15
| | | | | | | | | | Set up SRAT table in X2APIC mode when necessary. Change-Id: Ib8b4cebefe81f7b5514524dba2fa364eee4bb157 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* amdfwtool: Remove the option --list which nobody usesZheng Bao2023-03-103-29/+12
| | | | | | | | | | | | | It was used for printing the dependencies which is now taken by macro DEP_FILES in soc/amd/common/Makefile.inc. TEST=binary identical test on google/guybrush amd/chausie Change-Id: I1b86df2cb2ed178cf0a263c50ccb3e2254a3852b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73627 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amdfwtool: Move PSP FWs padding into a loop for comboZheng Bao2023-03-101-92/+106
| | | | | | | | | | | | | | | | | | | Move main body of PSP padding into a loop which can add a new combo entry. In the loop, get the FW files from each fw.cfg, create new pack of PSP, and fill the combo header. Currently Feature COMBO is still not fully functional. But the non-combo case will not be affected for sure. The real changes are 1. Add a do-while loop. 2. Remove a "TODO" comment. All other changes are re-indenting and re-filling. Change-Id: I351192a4bc5ed9ec0bfa3f2073c9633b8b44246d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58554 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/adl: Enable ASPMSean Rhodes2023-03-101-0/+5
| | | | | | | | | | Enable ASPM for RP5 (wireless) and RP9 (SSD). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I428040caf171bdcfedc285cdeddc55bcbec40f3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72753 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/var/markarth: Add 2 Micron parts to RAM ID tableJohn Su2023-03-103-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new ram_id:0011 for Micron MT62F1G32D2DS-023 WT:B. Add new ram_id:0100 for Micron MT62F2G32D4DS-023 WT:B. DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) MT62F1G32D2DS-023 WT:B 3 (0011) H58G66BK8BX067 4 (0100) MT62F2G32D4DS-023 WT:B 4 (0100) BUG=b:271188237 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I59a6a6dff249cd4fe982a4de824848f1bac0ecba Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73510 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spd/lp5: Add 2 Micron memory partsJohn Su2023-03-103-4/+30
| | | | | | | | | | | | | | | Add Micron memory part MT62F1G32D2DS-023 and MT62F2G32D4DS-023 to LP5 global list. Attributes are derived from CCM005-1974498342-145. Also, regenerate the SPD files for the SoC. BUG=b:271188237 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: I6675a68b7a515bd6d21db3ea2da762b06dee017a Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/omnigul: Fix SSD can not boot into OSJamie Chen2023-03-101-2/+3
| | | | | | | | | | | | | | 1. device ref pcie_rp11 -> pcie_rp9 on. BUG=b:270657362 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: If23785f42466ba94f33d4d15dde96de29dbb3a1e Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73530 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/omnigul: Enable ELAN touchscreenDtrain Hsu2023-03-101-0/+17
| | | | | | | | | | | | | | Enable ELAN eKTH5015M touchscreen. BUG=b:271966059 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I41eac949f21a48098b445f8d1b05f308672f7ab8 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/starlabs/starbook/{tgl,adl}: Set DmiMaxLinkSpeed to 4Sean Rhodes2023-03-102-0/+3
| | | | | | | | | | | Set DmiMaxLinkSpeed to 4 in FSP to ensure that FSP always supports PCIe Gen 4 drives. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0e31919122dacfbdc2486fa8216a28b479f3bd00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* amdfwtool: Add combo index and combo config tableZheng Bao2023-03-102-9/+40
| | | | | | | | | | | | | | For now, combo index is 0, and only the first entry in config table is used. The index will grow when there are more combo entries. Add a command parameter to give fw.cfg for combo index 1. Process the combo config in the future loop. Change-Id: I00609d91defc08e17f937ac8339575f84b1bd37c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* amdfwtool: Add a wrapper function to open and process config fileZheng Bao2023-03-101-20/+28
| | | | | | | | | | | And move the additional processing to this new function. Change-Id: Id101d63e4d30a6e57ac1aa79665a4ba22b2956f1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73509 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* amdfwtool: Add HW IPCFG file whose subprog is 1Zheng Bao2023-03-108-8/+12
| | | | | | | | | | And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/mediatek/mt8188: Enable lastbus debug hardwareot_zhenguo.li2023-03-1010-5/+245
| | | | | | | | | | | | | | | | | | | | | | Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out for bus hanging analysis. There are two versions for lastbus: Version 1 for MT8186, and version 2 for MT8188. BUG=b:263753374 TEST=build pass. Change-Id: Ibaf510481d1941376bd8da0168ef17c99a0fb9a2 Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73624 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* src/soc/amd/phoenix/include/soc/: Update the Data Fabric ID for PhoenixAnand Vaikar2023-03-101-1/+1
| | | | | | | | | | Change-Id: I078b57825377f97f9f5f2b607fa134e3a67e9685 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* Revert "mb/google/skyrim: Create whiterun variant"Jon Murphy2023-03-1010-472/+0
| | | | | | | | | | | | | | For simplicity, OEM devices are given a single codename per build variant. Winterhold was intended to be the lead device and was chosen as the code name for this OEM. Unfortunately, Winterhold was cancelled. We attempted to rename Winterhold to Whiterun to avoid future confusion. Again, unfortunately, since some devices were already built, changing the name requires a manual change to force the firmware to be taken by the DUT. This was not a reasonable path forward, so we're abandoning the naming to Whiterun. This reverts commit af69de494e2c32140ce5e00a1562c2845345b1bf. Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idef95f0f4f369b235937e1806ce57c427e441f21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73583 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/common/cpu: move get_threads_per_core from noncar to common codeFelix Held2023-03-092-7/+7
| | | | | | | | | | | | | | The get_threads_per_core function isn't specific to the non-CAR CPUs and also applies for Stoneyridge and even for family 16h model 30h outside of soc/amd, so move it from the non-CAR-specific cpu.c file to the common AMD SoC cpu.c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I05946f163112ff93f33139f6c43fed5820fd0a3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* device/Kconfig: explain which PCI ID needs to be used for VGA_BIOS_IDFelix Held2023-03-091-0/+4
| | | | | | | | | | | | Add a paragraph to the help text for VGA_BIOS_ID to explain which PCI ID needs to be used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1a0f25481e275b7d190f29f5670cc98443dbe719 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73613 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/common/cpu/Kconfig: use Cxxx as CPU string for all non-CAR SoCsFelix Held2023-03-092-4/+4
| | | | | | | | | | | | | | | | | Picasso already uses the Cxxx ACPI CPU device naming scheme, due to it being what the AGESA reference code uses. We initially relied on the AGESA/FSP generated SSDT for the P- and C-state support before we had a native implementation for this in coreboot. The Cxxx naming scheme can also be used for the other AMD SoCs except Stoneyridge which is pre-Zen and doesn't select SOC_AMD_COMMON_BLOCK_NONCAR. The main advantage of using Cxxx instead of CPxx is that the Cxxx scheme supports systems with more than 256 CPU threads. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I884f5c0f234b5a3942dacd60847b2f095f9c0704 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73620 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Add option to indicate uncompressed BIOS binaryKarthikeyan Ramasubramanian2023-03-091-0/+8
| | | | | | | | | | | | | | | | | | | amdfwtool always assumes that the PSP BIOS binary (type 0x62 BIOS directory entry) is always compressed. On boards using vboot, sometimes PSP BIOS binary is uncompressed - specifically when CBFS verification is enabled and verified boot starts in bootblock. Add an option to indicate PSP BIOS binary is uncompressed. BUG=b:261792282 TEST=Build Skyrim BIOS with x86 verstage and CBFS Verification enabled. Boot to OS. Change-Id: I4d56c0ba451b194043ebb5cdb0f2b27482beef1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/xeon_sp: rework lock_pam0123() to accomodate hidden SAD deviceJonathan Zhang2023-03-093-11/+17
| | | | | | | | | | | | | | For Intel SPR-SP, the SAD device is hidden, so pcidev_path_on_bus() returns NULL. Therefore use pci_s_write_config32() instead. Move lock_pam0123() from finalize.c to util.c, to be together with unlock_pam_regions(). Change-Id: Ib08d423d8c4d482612077b66dab3878018da8f2b Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* soc/intel/xeon_sp: use get_socket_ubox_busno() to hide soc specificsJonathan Zhang2023-03-097-16/+46
| | | | | | | | | | | Intel SPR-SP has its specific way to get the bus number of ubox. Move the current implementations to CPX-SP and SKX-SP folders. Change-Id: I2b69be74d140115f9f78bc991fb690e3c90c88db Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-14 08:50:31 +0000