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* device/pci_ops: Unify signaturesKyösti Mälkki2019-03-136-67/+67
| | | | | | | | | | Use fixed width types and const pointers for dev. Change-Id: Ide3b70238479ad3e1869ed22aa4fa0f1ff8aa766 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb/amd/cimx/sb800/early.c: Drop unused 'include <cbmem.h>Elyes HAOUAS2019-03-131-1/+0
| | | | | | | | Change-Id: I0e641197119588ccf090dad2950282f54ccbd208 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31857 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/stage_cache.c: Drop unnecessary includesElyes HAOUAS2019-03-134-12/+4
| | | | | | | | Change-Id: If6224c28012241e4925e05e14f0499857054f178 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* src/mainboard/*/*/cstates.c: Drop unused includesElyes HAOUAS2019-03-1316-22/+0
| | | | | | | | Change-Id: I315721d6261e558c3f7145c80714262052ce0e49 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31783 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.hElyes HAOUAS2019-03-138-13/+2
| | | | | | | | Change-Id: I1a0eed712e489b0fb63a7b650151646a56852d76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30321 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for CometlakeRonak Kanabar2019-03-122-1102/+1140
| | | | | | | | | | | | | Update header files for FSP for cometlake platform version 1065 BUG=b:125439832 Change-Id: I1eb679f842915f256137a33c09e20f5881d5143d Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS2019-03-1275-92/+4
| | | | | | | | | | Use <arch/acpi.h> when appropriate. Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPISubrata Banik2019-03-122-0/+13
| | | | | | | | | | | | Some new feature added into FSP specification to perform dispatching of external PPI service from boot firmware (coreboot) to FSP. Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/fsp2_0: Add provision to include PPI directorySubrata Banik2019-03-122-0/+14
| | | | | | | | | | | This patch adds a generic provision into FSP2.0 driver to implement dedicated PEIM to PEIM interface as per Intel FSP requirement. Change-Id: I988d55890f8dd95ccf80c1f1ec2eba8196ddf9a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Documentation/soc/intel: Add documentation for Intel FSPSubrata Banik2019-03-122-0/+14
| | | | | | | | | | | | This patch combines open source documentation for Intel FSP specification. Change-Id: I3a8bc0198a1e01ec019139b728834713978501ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31838 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/facebook/watson: Enable TPM 1.2 supportzaolin2019-03-122-1/+7
| | | | | | | | | | Enable TPM 1.2 via Kconfig options and devicetree. Change-Id: I394195b3117c8583b6b506d6ad4f5170d2f45f9f Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* mb/google/hatch: Add Hatch_whl boardShelley Chen2019-03-112-1/+8
| | | | | | | | | | | | | | | | | Adding Hatch_whl as a variant of hatch. This is a snapshot of the WHL version of hatch so that we can rebuild the bios images for Hatch with WHL SoC. BUG=b:127310803 BRANCH=NONE TEST=./util/abuild/abuild -p none -t google/hatch -x -a make sure HATCH_WHL is built as well. Change-Id: I24510fa226878582a61f1846f0b56a2c65204a92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/hatch: Enable audio supportSathya Prakash M R2019-03-113-4/+34
| | | | | | | | | | | | | | | | | | | | Following changes are done to enable audio support on hatch 1. Enable I2C4 device at 400Khz at 1.8V 2. Configure GPIO for HP INT and SPKR_PA_EN 3. Add ACPI entry for RT5682 and MAX98357A 4. Enable I2S0 and I2S1 lines 5. Enable generic max98357a driver in Kconfig BUG=b:123738217 BRANCH=none TEST=Check SSDT table for RT5682 & MAX98357a entry. Verify audio using Sound Open firmware (SOF) Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84 Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* vendorcode/google/chromeos: Fix AMAC return typeDuncan Laurie2019-03-111-2/+2
| | | | | | | | | | | | | | | The r8152 kernel driver is expecting the AMAC() method to return a raw buffer, not a string. To fix this simply remove the ToString() in the return statement that was converting the buffer to a string. BUG=b:123925776 Change-Id: I7cd4244a1ccc7397d5969b817a52ea48867b4d17 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31807 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Docs/project_ideas: Add a "parse SerialICE traces" project ideaPatrick Georgi2019-03-091-0/+22
| | | | | | | | Change-Id: I696811ff93948358f03ff617d294ecc40bd4c746 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Docs/project_ideas: Add a stub for Ghidra integrationPatrick Georgi2019-03-091-0/+7
| | | | | | | | | | | It may be useful to have a common, easily available toolbench for firmware analysis and Ghidra looks promising. Change-Id: I56d0ff875bb939f6d31f088232f8a6fd168abbb6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31806 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/efi/efi_datatype: Convert EFI datatypes as per coreboot specificationSubrata Banik2019-03-091-0/+87
| | | | | | | | | | | | | This patch replaces commonly used EFI datatypes and structures into coreboot compatible datatypes as below: typedef UINTN efi_uintn_t Change-Id: I79cdaaa1dd63d248692989d943a15ad178c46369 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* src/soc/intel/apollolake/cpu.c: Set up local APICMario Scheithauer2019-03-081-1/+5
| | | | | | | | | | | | | | Some Apollo Lake mainboards use SeaBIOS as payload. SeaBIOS requires the initialization of the programmable interrupt controller (PIC) for faultless operation. The PIC mode is need for USB support (e.g. keyboard, memory stick) and for some Option ROMs (e.g. PXE ROM). Therefore add setup_lapic() to configure the APIC. Change-Id: I00b339ce1850729023db74da7f8845927a95dcc6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31802 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/loglevel.h: Drop unnecessary includeElyes HAOUAS2019-03-0828-27/+2
| | | | | | | | | | This 'include' is only needed in console/console.h file. Change-Id: Ief61106eb78d0de743c920f358937c51658c228a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src/mb: Shorten 'include <arch/x86/include/arch/acpigen.h>'Elyes HAOUAS2019-03-0811-11/+11
| | | | | | | | | | 'include <arch/acpigen.h>' is good enough. Change-Id: Idc96376571715f5dd2c386f187b5c6d1613accee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31779 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Docs/project_ideas: Expand "toolchain" project descriptionPatrick Georgi2019-03-081-0/+6
| | | | | | | | | | | One-off packages do us little good, we need to be able to automate building them. Change-Id: Idd9b6b231435ea9d6e946c7ccaa71174b497742c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31804 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lint/kconfig: Update to support new CONFIG() macroJulius Werner2019-03-081-16/+37
| | | | | | | | | | | | | | | This patch updates the Kconfig linter to support the new CONFIG() macro in the same manner that IS_ENABLED() was previously supported. It will be flagged when it is used on non-bool Kconfigs or used with #ifdef, and it is supported for checking used Kconfigs. Remaining uses of IS_ENABLED() are flagged with a deprecation warning. Change-Id: I171ea8bc8e2d22abab7fc4d87ff4cf8aad21084f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31776 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-08920-2285/+2285
| | | | | | | | | | | | This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation: Our coding style now allows 80 + 2*8 columns in a linePatrick Georgi2019-03-081-4/+9
| | | | | | | | | | | Update the document to match clang-format and checkpatch formally, and provide a rationale. Change-Id: I597a27d4e22d07e033b36f0dceb554ac1d8d5789 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* mb/google/hatch: Create hatch_whl variantShelley Chen2019-03-083-0/+58
| | | | | | | | | | | | | | | | In preparation for the transition of hatch from WHL to CML, we are creating a checkpoint called hatch_whl that we can use for creating firmware compatible with the WHL hatch variant. BUG=b:127310803 BRANCH=NONE TEST=NONE Change-Id: Iecae584ee6feefcf29955a4720e9c24bdc8abe6d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/hatch: Initialize all gpiosShelley Chen2019-03-081-98/+314
| | | | | | | | | | | | BUG=b:123490912 BRANCH=None TEST=flash BIOS and make sure hatch boots up properly Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31724 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Add support for logging wake source in SMMV Sowmya2019-03-072-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for logging wake source information in gsmi callbacks. With this change, all the elog logging infrastructure can be used for S0ix as well as S3 on cannonlake. BUG=b:124131938 BRANCH=none TEST=Verified that the wake events are logged during the S0ix resume: 6 | 2019-03-04 17:03:13 | S0ix Enter 7 | 2019-03-04 17:03:17 | S0ix Exit 8 | 2019-03-04 17:03:17 | Wake Source | RTC Alarm | 0 9 | 2019-03-04 17:03:55 | S0ix Enter 10 | 2019-03-04 17:03:56 | S0ix Exit 11 | 2019-03-04 17:03:56 | Wake Source | GPE # | 21 12 | 2019-03-04 17:04:36 | S0ix Enter 13 | 2019-03-04 17:04:45 | S0ix Exit 14 | 2019-03-04 17:04:45 | Wake Source | GPE # | 112 15 | 2019-03-04 17:05:01 | S0ix Enter 16 | 2019-03-04 17:05:09 | S0ix Exit 17 | 2019-03-04 17:05:09 | Wake Source | Power Button | 0 Change-Id: Id627843e22c2524dfa94395b780cf2134f386137 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/cannonlake: Move power_state functions to pmutil.cV Sowmya2019-03-073-89/+64
| | | | | | | | | | | | | | | This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm. BUG=b:124131938 BRANCH=none TEST=none Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* src/device/Kconfig: Include the discrete VGA OpROM at config UIMike Banon2019-03-072-0/+40
| | | | | | | | | | | | | Create the way of adding the discrete VGA OpROM at config UI (alternative to ./cbfstool ./cb.rom add -f vgabios_dgpu.bin -n pci1002,6663.rom -t optionrom ) DGPU options are accessible only if CONFIG_VGA_BIOS is enabled. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0a7bf0fe95c833cf3df0c7cb20fc27b6ab218c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/31449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* intelmetool: Add more flag descriptionsDamien Zammit2019-03-072-0/+6
| | | | | | | | | | | | Obtained by inspecting intel SPSinfo tool output Change-Id: I69eb0dd86761984b6f0a450b7d8757268b0b248e Author: roncapat Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31589 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intelmetool: Consolidate all model support from upstreamDamien Zammit2019-03-072-67/+273
| | | | | | | | | | | | | Some of the older chipsets that are known not to have ME at all were removed for some reason, add them back in. Also some newer chipsets/ME models were missing, add them in. Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if existSubrata Banik2019-03-072-1/+7
| | | | | | | | | | | | | | | | | | | This patch adds timestamp for "end of romstage" with postcar if platform has selected postcar as dedicated stage. If postcar stage doesn't exist then "end of romstage" timestamp will get call while starting of ramstage as exist today. TEST=It's been observed that "end of romstage" timestamp doesn't appear in "cbmem -t" log when ramstage is not getting executed. As part of this fix "end of romstage" timestamp is showing in "cbmem -t" log on Intel platform where POSTCAR is a dedicated stage. Change-Id: I17fd89296354b66a5538f85737c79145232593d3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* arch/x86/postcar: Add separate timestamp for postcar stageSubrata Banik2019-03-073-0/+10
| | | | | | | | | | | | | | | | | | | This patch adds dedicated timestamp value for postcar stage. TEST=Able to see "start of postcar" and "end of postcar" timestamp while executing cbmem -t after booting to chrome console. > cbmem -t 951:returning from FspMemoryInit 20,485,324 (20,103,067) 4:end of romstage 20,559,235 (73,910) 100:start of postcar 20,560,266 (1,031) 101:end of postcar 20,570,038 (9,772) Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/icelake: Add PM timer emulation support in ICLAamir Bohra2019-03-072-0/+24
| | | | | | | | | | | | | | | CPU PM TIMER EMULATION logic will help UEFI payload to execute rather wait for time tick in absence of TCO and ACPI PM timer after FSP-S. BUG=N/A TEST=Able to build and boot with tianocore payload. Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/{asus/p5qc,intel/dg43gt}: Remove unneeded include i82801jx.hElyes HAOUAS2019-03-073-4/+2
| | | | | | | | | Change-Id: Ia1e64c750dfa6901ac7c9e786952eed49cccfa17 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* vboot: rename VB2_DISABLE_DEVELOPER_MODEJoel Kitching2019-03-071-1/+1
| | | | | | | | | | | | | | | | Rename VB2_DISABLE_DEVELOPER_MODE to VB2_CONTEXT_DISABLE_DEVELOPER_MODE. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460645 BRANCH=none Change-Id: Ib9754425dc2f346e8edac584c4d076d13ae31d2d Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* vboot: rename VB2_SD_DEV_MODE_ENABLEDJoel Kitching2019-03-071-1/+1
| | | | | | | | | | | | | | | | Rename VB2_SD_DEV_MODE_ENABLED to VB2_SD_FLAG_DEV_MODE_ENABLED. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460644 BRANCH=none Change-Id: I298cd3a5026055e439de1ce409e61f1feb24369b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* src: Drop unused include <timestamp.h>Elyes HAOUAS2019-03-0728-29/+0
| | | | | | | | Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* 3rdparty/blobs: Update submodule pointerNico Huber2019-03-071-0/+0
| | | | | | | | | | | | * Update SMU firmware for amd/stoneyridge * Remove stale Sandy Bridge MRC binaries Change-Id: Ifd1a9f02d96bc7cf5d23706a09634c0353dfae61 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-0761-176/+176
| | | | | | | | | | | | | This patch is a raw application of find payloads/ -type f | \ xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Docs/project_ideas: Add coverity scan cleanup projectPatrick Georgi2019-03-071-0/+20
| | | | | | | | | Change-Id: I16d9a7f7088254c5c207adc9299a8525bf38199f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Add myself as potential mentor for QEMU targetsPatrick Georgi2019-03-071-0/+1
| | | | | | | | | Change-Id: I11df0283f14ae03243247fe9377754b216df0442 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31556 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add new CONFIG(XXX) macro to replace IS_ENABLED(CONFIG_XXX)Julius Werner2019-03-072-2/+6
| | | | | | | | | | | | | | | | | | | | | | The IS_ENABLED() macro is pretty long and unwieldy for something so widely used, and often forces line breaks just for checking two Kconfigs in a row. Let's replace it with something that takes up less space to make our code more readable. From now on, if (IS_ENABLED(CONFIG_XXX)) #if IS_ENABLED(CONFIG_XXX) shall become if (CONFIG(XXX)) #if CONFIG(XXX) Change-Id: I2468427b569b974303084574125a9e1d9f6db596 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mainboard/google/kahlee: Add additional Micron MT40A512M16TB-062E:J SPD for ↵Kevin Chiu2019-03-072-1/+34
| | | | | | | | | | | | | variants BUG=b:127394249 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage Change-Id: Ibb4beddf186233fd82ec8f3a01bf14d00b1352ff Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31778 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Remove fanless SMU optionsMarshall Dawson2019-03-071-17/+1
| | | | | | | | | | | | | | | Complete the removal of the fanless command line options. The only soc using them has been converted to use the subprogram option instead. TEST=Verify amdfw.rom is unchanged before and after the conversion BUG=b:126691068 Change-Id: I187f17743cc98cc136b0df61caf8e95d17f98d51 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31737 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/stoneyridge: Convert SMU fanless optionsMarshall Dawson2019-03-071-2/+3
| | | | | | | | | | | | | | | Change the amdfwtool command line arguments to use the new --subprogram option. TEST=Verify amdfw.rom is unchanged before and after the conversion BUG=b:126691068 Change-Id: Iaae4094251974b8dad48b8d2c37bb2e43a412237 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31736 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Split type field for PSP entriesMarshall Dawson2019-03-071-29/+67
| | | | | | | | | | | | | | | | | | | | | | | | Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Streamline functions with contextMarshall Dawson2019-03-071-66/+105
| | | | | | | | | | | | | | | | | Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* util/amdfwtool: Add generic image copy functionMarshall Dawson2019-03-071-65/+43
| | | | | | | | | | | | | | Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* util/amdfwtool: Combine table header populationMarshall Dawson2019-03-071-22/+26
| | | | | | | | | | | | | Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 04:23:05 +0000