summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* soc/intel/alderlake: Set FSP-S GnaEnable based on devicetreeJeremy Soller2022-09-161-0/+7
| | | | | | | | | | Change-Id: Ifd25416c55c4dba1709f74cdedc0c58e881d6266 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/kconfig/regex.c: Remove leftoverElyes Haouas2022-09-161-5/+0
| | | | | | | | | | coreboot doesn't support the MIPS architecture anymore. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I404d034949a7786d7971117081537baf27ff2e22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* crossgcc [binutils]: Remove 'enable-plugins' optionElyes Haouas2022-09-161-2/+2
| | | | | | | | | | | unneeded 'enable-plugins' option sneaked in..., so remove it. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id1d7f2c7e6b70c28e1060c6ee915363ffe412ef6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* crossgcc [binutils]: Remove invalid enable-interwork optionElyes Haouas2022-09-161-2/+1
| | | | | | | | | | | | 'enable-interwork' is not a binutils configure option. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I29cd6137c700ff6871868a723daf33909aa218ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65609 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* drivers/usb/hub/acpi.c: Don't use heap for ACPI nameArthur Heymans2022-09-162-5/+10
| | | | | | | | | | | | | | | | Using malloc would increase the heap use each time this function is called. Instead allocate a per struct device buffer inside the chip_info struct. Found by coverity scan, CID 1488815. Change-Id: Ie24870b34338624b3bf3a6f420debdd24a68ffbd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64338 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/nissa/var/nivviks: Enable nau8825 ADCOUTEric Lai2022-09-161-0/+1
| | | | | | | | | | | | | Enable nau8825 ADCOUT to make I2S signal meet spec. BUG=b:234789689 TEST=I2S waveform can meet spec timing. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7ea472ac4e4add4e790b9b3fbb6becd40665eb1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* drivers/i2c/nau8825: Add ADCOUT IO drive strength controlEric Lai2022-09-162-0/+6
| | | | | | | | | | | | | Add a property to control the driving of ADCOUT. BUG=b:234789689 TEST= build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ibbedd5838a795ee645a5458b960062c5530ff3b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/intel/common: Update comment on HFSTS1.spi_protection_modeSridhar Siricilla2022-09-161-5/+7
| | | | | | | | | | | | | | | | | | | The patch updates comment on HFSTS1.spi_protection_mode. The spi_protection_mode indicates SPI protection status as well as EOM status (in a single staged EOM flow). Starting from TGL platform, staged EOM flow is introduced. In this flow, spi_protection_mode alone doesn't indicate the EOM status. For information on EOM status, please refer secton# 3.6.1 in doc# 612229. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* contributing/coding_style.md: Add missing ">"Elyes Haouas2022-09-161-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I2f2cd20139f4cdb7ba665e9e49a03faea1ac085b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"Subrata Banik2022-09-163-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 510a55d4eeaeb32047c17328ef238b55b89e7296. Reason for revert: Observed `missing read resource` issue for cnvi device BUG=b:244687646 TEST=No error seen in AP log while booting Google/rex Without this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [ERROR] GENERIC: 0.0 missing read_resources [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done With this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1e881313729f1088cffa7c161722ee79bb9acc49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67566 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* soc/intel/meteorlake: Enable `SOC_INTEL_COMMON_BLOCK_CNVI` configSubrata Banik2022-09-161-0/+1
| | | | | | | | | | | | | TEST=Able to build and boot Google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I64aab8391f89414754785cea47671f3350324297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/rex: Enable `DRIVERS_WIFI_GENERIC` configSubrata Banik2022-09-161-0/+1
| | | | | | | | | | | | | TEST=Able to build and boot the Google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iae5317b24856ef2cbd2f36cc28f645826536c21a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* amd/mendocino: Control DPTC with only KconfigTim Van Patten2022-09-152-7/+3
| | | | | | | | | | | | | | | | | | | | | SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any skyrim boards, similar to mainboard/google/zork/Kconfig. This makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=emerge-skyrim coreboot Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I73fca5a16826313219247f452d37fb526ad4f4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/67639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amd/cezanne: Control DPTC with only KconfigTim Van Patten2022-09-152-7/+3
| | | | | | | | | | | | | | | | | | | | | SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any guybrush boards, similar to .mainboard/google/zork/Kconfig This makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=emerge-guybrush coreboot Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I07f1266fa80a6c9ee4ec3b3ba970a70c6c72fb54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* zork: Control DPTC with only KconfigTim Van Patten2022-09-153-9/+3
| | | | | | | | | | | | | | | | | | | | | Moving the config value SOC_AMD_COMMON_BLOCK_ACPI_DPTC to soc/amd/picasso/Kconfig and conditionally enabling it for only Morphius boards makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=Build zork Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ic54a9bb491234088be8184bec8b09e2e31ffa298 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd: Do SMM relocation via MSRArthur Heymans2022-09-155-12/+37
| | | | | | | | | | | | | | | | | | | AMD CPUs have a convenient MSR that allows to set the SMBASE in the save state without ever entering SMM (e.g. at the default 0x30000 address). This has been a feature in all AMD CPUs since at least AMD K8. This allows to do relocation in parallel in ramstage and without setting up a relocation handler, which likely results in a speedup. The more cores the higher the speedup as relocation was happening sequentially. On a 4 core AMD picasso system this results in 33ms boot speedup. TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM is correctly relocated with the BSP correctly entering the smihandler. Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/skylake: Assign device ops in chipset devicetreeNico Huber2022-09-1519-272/+94
| | | | | | | | | | | | | | | | | | | | | | | Some PCI IDs were missing, and at least one (SPT's fast SPI device in a generic SPI driver) was wrong. Hence, this patch actually changes behavior depending on the devices actually present in a machine. In this patch the Skylake devicetree is written in a single-line style. Alternative, the device operations could be put on a separate line, e.g. device pci 00.0 alias system_agent on ops systemagent_ops end Tested on Kontron/bSL6. Notable in the log diff is that the CSE and SATA drivers are hooked up now. Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sconfig: Allow to specify device operationsNico Huber2022-09-157-344/+413
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we only have runtime mechanisms to assign device operations to a node in our devicetree (with one exception: the root device). The most common method is to map PCI IDs to the device operations with a `struct pci_driver`. Another accustomed way is to let a chip driver assign them. For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI ID lists grew very large and are incredibly error-prone. Often, IDs are missing and sometimes IDs are added almost mechanically without checking the code for compatibility. Maintaining these lists in a central place also reduces flexibility. Now, for onboard devices it is actually unnecessary to assign the device operations at runtime. We already know exactly what operations should be assigned. And since we are using chipset devicetrees, we have a perfect place to put that information. This patch adds a simple mechanism to `sconfig`. It allows us to speci- fy operations per device, e.g. device pci 00.0 alias system_agent on ops system_agent_ops end The operations are given as a C identifier. In this example, we simply assume that a global `struct device_operations system_agent_ops` exists. Change-Id: I2833d2f2450fde3206c33393f58b86fd4280b566 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/xeon_sp: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-1510-33/+33
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I664f5b7d354b0d9a7144c25604ae4efbdd9ba9a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* mb/ocp: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-151-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie5fc0a8230cdcc24ad1d2d94cc6d019ff10aac48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* soc/intel/meteorlake: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-152-3/+3
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia2508abe62a194f2921d5535937ba82a60967ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* src/security: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-156-10/+10
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I3def65c016015d8213824e6b8561d8a67b6d5cf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/mistral/verstage.c: Change loglevel prefixElyes Haouas2022-09-151-1/+1
| | | | | | | | | | | BIOS_ERR is inappropriate since the message is informational. Use BIOS_INFO instead. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I91be3f47ae93c8262e430a06cacec3d2c29ebd58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/ifittool: Error out if microcodes do not fit the FIT tableJeremy Compostella2022-09-151-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | parse_microcode_blob() returns success when it reaches max_fit_entries microcode. It makes the FIT table size verification in fit_add_microcode_file() useless. This patch makes parse_microcode_blob() error out if max_fit_entries is reached. Note that this size verification is critical as a FIT table only partially listing the microcode patches can lead to boot failures as recently observed on Raptor Lake-P. BRANCH=firmware-brya-14505.B BUG=b:245380705 TEST=compilation errors out when trying to stitch more than CONFIG_CPU_INTEL_NUM_FIT_ENTRIES microcode patches. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fde Reviewed-on: https://review.coreboot.org/c/coreboot/+/67454 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
* cpu/intel/haswell: Allow up to six microcodes in the FIT tableJeremy Compostella2022-09-151-0/+3
| | | | | | | | | | | | | | | | Haswell and Broadwell platforms usually stitch six microcode patches. It has worked so far with the default value of four thanks a bug which is being fixed by `util/ifittool: Error out if microcodes do not fit the FIT table' commit. BUG=b:245380705 TEST=Jenkins build without failing on the FIT table size Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I23bf79a3e8918499f6c51e6ef829312d5872181a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* zork/Kconfig: Move SOC_AMD_COMMON_BLOCK_ACPI_DPTCTim Van Patten2022-09-142-1/+1
| | | | | | | | | | | | | | | | | | | | Move enabling SOC_AMD_COMMON_BLOCK_ACPI_DPTC from soc/amd/picasso/Kconfig to mainboard/google/zork/Kconfig and conditionally enable it only for Morphius boards. This reduces which boards/variants have DPTC enabled to only those that actually use it. BRANCH=none BUG=b:217911928 TEST=Build zork Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Iddebcf5dbadae135c8110e2afd9ad76ef7dcc09d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67637 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/soc: Conditionally include dptc.aslTim Van Patten2022-09-143-0/+6
| | | | | | | | | | | | | | | | | | | Conditionally include dptc.asl based on the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim TEST=Build majolica Change-Id: Idd94af8e8b2d7973abc0fb939e4600189e21656a Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67620 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne/Kconfig: add defaults for FSP_M_FILE and FSP_S_FILEFelix Held2022-09-141-0/+14
| | | | | | | | | | | | Now that the FSP binary check logic is fixed to only check the FSP files if ADD_FSP_BINARIES is selected, the default paths for the not yet published Cezanne FSP binaries can be added without breaking abuild. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9950a1fe7bd1b21109cca9631de1a8f1d265d9b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/fsp: only check FSP_M size if ADD_FSP_BINARIES selectedFelix Held2022-09-141-4/+2
| | | | | | | | | | | | Only check if the FSP_M size is small enough to fit inside the memory region reserved for it if ADD_FSP_BINARIES selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I6a115412c113eb0d02b8d4dfc2bb347305f97809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/lint: Add a check for touchpads using the "probed" flagMatt DeVillier2022-09-141-0/+29
| | | | | | | | | | | | | | | | | As of commit 2cf52d80a6ec ("mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flag") all touchpads in the tree have been switched from using the 'probed' flag to 'detect.' Add a lint check to ensure no touchpads are added with the probed flag. TEST=manually change one touchpad to use 'probed' flag and ensure lint check catches it. Change-Id: Ie0aee2e3778fc56c6c21c97995738a147a1fa0d4 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67486 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/amd/gardenia: deselect HAVE_PIRQ_TABLE and drop incorrect irq_tablesFelix Held2022-09-142-87/+0
| | | | | | | | | | | | | This file isn't correct, since the Stoneyridge SoC doesn't have a legacy PCI bridge on bus 0 bridge 0x14 function 4. Google/Kahlee doesn't select HAVE_PIRQ_TABLE, so it's likely safe to also not select it for this board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf470b9ff7823019772d43af98ebc47af395728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/kahlee: drop unused and incorrect irq_tables.cFelix Held2022-09-141-86/+0
| | | | | | | | | | | | This file is neither included in the build nor correct, since the Stoneyridge SoC doesn't have a legacy PCI bridge on bus 0 bridge 0x14 function 4. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0daed891984faed9fbc36f0215edfc56e0ae14a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/skyrim/winterhold: Use 'detect' vs 'probed' for touchpadsMatt DeVillier2022-09-141-2/+2
| | | | | | | | | | | | | | | As of commit 2cf52d80a6ec ("mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flag") all touchpads in the tree have been switched from using the 'probed' flag to 'detect.' Winterhold was added in between the time that patch was pushed and merged, so switch these instances over too. Change-Id: I34e1265ecd6409f720ae486926c5078f626fc693 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67487 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/amd: Move locking SMM as part of SMM initArthur Heymans2022-09-144-38/+11
| | | | | | | | | | | | Locking SMM as part of the AP init avoids the need for CONFIG_PARALLEL_MP_AP_WORK to lock it down. Change-Id: Ibcdfc0f9ae211644cf0911790b0b0c5d1b0b7dc9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64871 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/amd/smm: Move MP & SMM init in a common placeArthur Heymans2022-09-146-140/+38
| | | | | | | | Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common: Add common function to get cpu countArthur Heymans2022-09-149-21/+21
| | | | | | | | | | | This is the same for all supported AMD hardware. Change-Id: Ic6b954308dbb4c5a2050f1eb8f15acb41d0b81bd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67617 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd: Recalculate the field power in PSS table entryZheng Bao2022-09-143-9/+12
| | | | | | | | | | | | | | | | | Being divided by 1000 causes data loss and the loss is expand by muliplication. So we just set a lower divisor before muliplication. BUG=b:185922528 Change-Id: Ib43103cc62c18debea3fd2c23d9c30fb0ecd781b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* 3rdparty/opensbi: Update to latest ToTPatrick Georgi2022-09-143-1/+2
| | | | | | | | | | | | | | | That's 3 years of development, including adapting to new, shiny, Cascade of Attention-Deficit Teenagers[0] induced incompatible assembler syntaxes. Signed-off-by: Patrick Georgi <patrick@coreboot.org> [0] https://web.archive.org/web/20220824045741/https://www.jwz.org/doc/cadt.html Change-Id: I8606700149ca74e93b85d78546a29df2916d39b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/amd/mendocino: Add support for separate RW A/B partition SPL fileFelix Held2022-09-142-1/+24
| | | | | | | | | | | | | | | | | Add support for having different Security Patch Level (SPL) table files in the read-only and the read-write A/B partitions. This allows the SPL table file in the main or RO FMAP partition to only cover the embedded firmware binaries in that partition and have a separate SPL file in the RW A and B partitions that covers the embedded firmware binaries in the RW partitions. BUG=b:243470283 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ba8c370ce14f7ec88e7ef2f9d0b64d6bb4fa176 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/dedede/variants/shotzo: Turn off LAN power in S0ixTony Huang2022-09-142-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Turn off the LAN power which is controlled by GPP_A10 in S0ix states. For an USB device, the S0ix hook is needed for the on/off operationas to take place. BUG=b:245426120 BRANCH=firmware-dedede-13606.B TEST=emerge-shotzo coreboot check LAN LED off in S0ix states check LAN function ok after suspending 500 loops check SSDT table has MS0X entry Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x41) } Else { \_SB.PCI0.STXS (0x41) } } } Change-Id: I3fcab4a73239b4f006839c0c81e9b4cc74047b77 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* crossgcc: binutils: Remove invalid enable-multilibs optionElyes Haouas2022-09-141-1/+1
| | | | | | | | | | | | | | Looks like somewhere after the original implementation it was renamed to --enable-multilib without the s. 'enable-multilibs' is not a valid option for binutils. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I105cc9fa489aed24905dedb785c70bc69ed18970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65608 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/intel/cannonlake: Read HPR_CAUSE0 registerAngel Pons2022-09-143-0/+5
| | | | | | | | | | | Log the Host Partition Reset Causes (HPR_CAUSE0) register, as done on newer platforms. Change-Id: I35261cefae67649fb7824e5ef3d7eb10add36a53 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* console/vtxprintf.c: Use | operator for bit operation instead of +Elyes Haouas2022-09-141-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I478265dcd070dcf3fb2cf2c535b6ca1d86b9a3f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/mediatek: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-145-7/+7
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I9cf4097518034fa4c3ae1899840ae3a276936f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67581 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-149-9/+9
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6d0d945011fa046b974c6f4554cb9fb15e523afb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67578 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Set PLLs to hardware default valuesGarmin Chang2022-09-141-84/+84
| | | | | | | | | | | | | | | Some PLLs are not used in firmware, so we should keep them as hardware default values. If their modules want to set them, the corresponding drivers should set them in the kernel stage. BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I9bee18005ffed7fc1785c7fd3c0370c8293064ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/67547 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Fix indention in pll.cGarmin.Chang2022-09-141-1/+1
| | | | | | | | | | | BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: I567d1ded1c3b5e36a25026cec697d43d92d5524c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67546 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Change vpp_sel default mux for 4k supportGarmin Chang2022-09-141-2/+2
| | | | | | | | | | | | | | | | | vpp_sel and ethdr_sel are vdosys clock source select mux. Steps to change to support 4K source: 1. Change vpp_sel source to mainpll_d6 to run at 416MHz. 2. Change ethdr_sel source to univpll_d6 to run at 416MHz. BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I24f133b9b383fd019983cb29a213b47717148e97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67545 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Raise little core CPU frequency from 500MHz to 2GHzRex-BC Chen2022-09-142-0/+19
| | | | | | | | | | | | | | | | | To improve boot time, raise little CPU from 500MHz to 2GHz at romstage (before DRAM calibration). FW logs: Check CPU freq: 1999968 KHz, cci: 1600012 KHz TEST=cpu freq and cci freq run correctly. BUG=b:244251006 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ic1bed53669baa15f797c9a952455376a39d29cf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67544 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Fix some wrong settings for PLLsGarmin Chang2022-09-141-18/+18
| | | | | | | | | | | | | | | | | The observed CPU big core frequency is double compared with the current PLL setting. Therefore fix the wrong setting for PLL register APMIXED_ARMPLL_BL. Moreover, we also fix some wrong settings for other PLLs. TEST=CPU frequency of big core CPU is correct and bootup correctly. BUG=b:244215537 Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I9126f439d7a5136b2fb8d66f103ef427a0b08a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67543 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 06:26:50 +0000