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* mb/google/brya: Create volmar variantDavid Wu2022-01-108-0/+46
| | | | | | | | | | | | | | | | | | Create the volmar variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:213127419 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_VOLMAR Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I5ebf62b7a17b075c0e28fb4e8b7c501fc8db3ea3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/agah: move memory makefile to correct pathTony Huang2022-01-104-33/+27
| | | | | | | | | | | | | Move memory Makefile.inc and dram_id.generated.txt to correct path BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: Ib5d9d9dd6f881f0b9cf2736809a74e5045c3c217 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/hatch/var/scout: Update DPTF parametersKenneth Chan2022-01-101-5/+5
| | | | | | | | | | | | | | Update the DPTF parameters received from the thermal team. Refer to https://partnerissuetracker.corp.google.com/issues/195602767#comment6. BUG=b:195602767 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I93fe388ff1862d0a96b11ce68a5d28664f11996a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer/var/chronicler: add Elan touch supportSheng-Liang Pan2022-01-101-0/+15
| | | | | | | | | | | | | | Enable Elan touchscreen support for chronicler. BUG=b:213537197 TEST=emerge-volteer coreboot chromeos-bootimage verified touchscreen works Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ic56092972eb9555b097b21ff5828573926610f31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* southbridge/amd/agesa/hudson/smi_util.c: Remove repeated "set"Elyes HAOUAS2022-01-101-1/+1
| | | | | | | | Change-Id: I6741084651a9472162cf549a4170e954e760f0f1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* southbridge/amd/pi/hudson/smi_util.c: Remove repeated "set"Elyes HAOUAS2022-01-101-1/+1
| | | | | | | | Change-Id: Ice47aeb9b1bc462d60b396bedeaab48ae0922e00 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* mb/google/brya: Use genesyslogic gl9755 SD card reader for FelwinterEric Lai2022-01-101-0/+1
| | | | | | | | | | | | | | Felwinter selects DRIVERS_GENESYSLOGIC_GL9755 Kconfig to make use of SD card reader driver. BUG=b:209501017 TEST=build PASS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I196ae9c5dbbcc6057d17605eece27563bcc79af8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60893 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entriesMichael Niewöhner2022-01-094-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Enable CPPC entries generation, needed for Intel SpeedShift. This can be tested by checking sysfs in Linux: $ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf The output should look like this, while the values may differ: /sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1 /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24 /sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5 ... Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
* soc/intel/xeon_sp: Don't handle FSP reserved memory explicitlyArthur Heymans2022-01-081-31/+3
| | | | | | | | | | | | FSP reserved memory is allocated inside cbmem which already gets marked as a reserved memory region, so there is no need to do this explicitly. Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* configs: Add build test configs for CBFS verificationJulius Werner2022-01-082-0/+9
| | | | | | | | | | | | | Now that CBFS verification is available as an optional feature in menuconfig (CB:59982), we should add build test configs to ensure it doesn't break without notice. One Arm and one x86 board should be good enough for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I530dfd37472e63b80a67badd22a13d54d2c4621b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* sc7180: Increase bootblock size and add pre-RAM TCPA bufferJulius Werner2022-01-081-2/+3
| | | | | | | | | | | | | | In order to make SC7180 boards compatbile with some optional Kconfigs, increase the bootblock size a bit and add room for a TCPA log buffer to memlayout. The large pre-RAM CBFS cache wasn't really needed anymore anyway since we switched QcLib to use LZ4 compression. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7321cca9d7b79368115c57f156b8e71657802a41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com>
* mb/google/herobrine: Add support for audioSrinivasa Rao Mandadapu2022-01-083-0/+21
| | | | | | | | | | | | | | Add GPIO configuration for target specific i2s ports. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Boot on herobrine board (no speakers to test yet) Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/herobrine: Initialize EC and TPM devicesShelley Chen2022-01-074-8/+81
| | | | | | | | | | | | | | | Initialize EC and H1/TPM instances on herobrine devices. BUG=b:182963902 BRANCH=None TEST=Validated on qualcomm sc7280 development board and verified booting on herobrine. Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/vell: Add MIPI camera infoShon Wang2022-01-073-0/+73
| | | | | | | | | | | | | | Add OVTI8856 information for vell: BUG=b:210801553 TEST=Build and boot on vell Change-Id: I43de859cd0cdd9fe21c16cabfad511ed0b368ee3 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/vell: Swap TPM I2C with touchscreen I2CShon Wang2022-01-073-8/+29
| | | | | | | | | | | | | | | | According to the latest schematic for the next build phase, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:210572663 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: If72717a2c073f5b871c3109399f466a04a9d2484 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/taniks: Change probe for audio 4 channel speakerJoey Peng2022-01-072-5/+5
| | | | | | | | | | | | | | Taniks only uses 4 channel speakers. Change the probe name to match SOF topology settings. BUG=b:207808510 TEST=dmidecode -t 11 shows correct audio fw_config. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2986bd212cef47f70dfeedc642a8db3314c947f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPsTim Wawrzynczak2022-01-071-11/+29
| | | | | | | | | | | | | | | | | | | | | | | The PMC IPC method that is used for RTD3 support expects to be provided the virtual wire index instead of the LCAP PN for CPU PCIe RPs. Therefore, use the prior patches to update pcie_rp for CPU RPs. Note that an unused argument to pcie_rtd3_acpi_method_status() was also dropped. BUG=b:197983574 TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and inspect the SSDT to see the PMC IPC parameters are as expected for the CPU RP, and the ModPhy power gating code is not found in the AML for the PEG port. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Crawford <tcrawford@system76.com> Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60183 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDsTim Wawrzynczak2022-01-071-0/+22
| | | | | | | | | | | | The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe ports, but the UPDs are not set. This patch hooks up those config structs to the appropriate FSP-S UPDs. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/intel/common/blk/memory: Make mixed topo workAngel Pons2022-01-071-5/+10
| | | | | | | | | | | | | | | | | | When using a mixed memory topology with DDR4, it's not possible to boot when no DIMMs are installed, even though memory-down is available. This happens because the DIMM SPD length defaults to 256 when no DIMM SPD is available. Relax the length check when no DIMMs are present to overcome this problem. Tested on system76/lemp10. Unit boots with and without DIMM installed. Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Tested-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
* mb/google/dedede/var/boten: Add Wifi SAR for bookemStanley Wu2022-01-071-3/+14
| | | | | | | | | | | | | | Add new sku id apply for bookem wifi sar table. BUG=b:211705077 TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I1e5bac662fb44cf631ae1453068dec898b6e2607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/mediatek/mt8186: fix incorrect devapc settingsRunyang Chen2022-01-072-9/+9
| | | | | | | | | | | | | | | | | | | | | We need to protect debugsys for firmware image without serial console. Original settings for protecting debugsys is wrong which will cause some hardware modules to fail to set their registers correctly. We move the setting from MM_AO_APC to INFRA_AO_APC because the setting of debugsys is defined in INFRA_AO_APC and set the debugsys index to correct value of 94. BUG=b:213125558 TEST=all modules work normally using image without serial console. Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: Ibce626386ac1f8de42f8717c4ad9ba403640b3ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60833 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: initialize DFDRex-BC Chen2022-01-073-0/+24
| | | | | | | | | | | | | | | | DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7b711755022b5d9767019611151fea65e71edc66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60828 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/corsola: Enable the SD card readerRex-BC Chen2022-01-073-2/+9
| | | | | | | | | | | | | | The Kingler board has an SD card reader connected via USB and can be enabled by setting GPIO EN_PP3300_SDBRDG_X to output mode and activated. BUG=b:211385131 TEST=boot kernel using SD card. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I903731ea4906328b2f0f5a7c6c06bd9c964d24ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60780 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/redrix: Tune I2c frequencyWisley Chen2022-01-071-0/+18
| | | | | | | | | | | | | | | | | | | Tune the I2c frequency I2C0 - 391 kHz I2C1 - 391 Khz I2C2 - 393 kHz I2C3 - 394.7 KHz I2C5 - 399.6 KHz BUG=b:213298209 TEST=build Change-Id: Id15c5298f8917bac404026f1ecb000fa7f925416 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/anahera: Fine tune I2C frequencyWisley Chen2022-01-071-0/+12
| | | | | | | | | | | | | | | | | Fine tune i2c frequency. I2C0 - 399.6 kHz I2C1 - 391.4 kHz I2C3 - 398.1 kHz I2C5 - 399.9 kHz BUG=b:213295817 TEST=build Change-Id: I9a89820a8d9ae4c9b4ee499e8467426e0670656d Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/anahera: Swap TPM I2C with touchscreen I2CWisley Chen2022-01-073-25/+21
| | | | | | | | | | | | | | | According to the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:212465011 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I1bb1857b4c5b06ca4ad660bf73e0c4df9c376a58 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/ipmi: Change type of custom_count from int to size_tPaul Menzel2022-01-071-3/+3
| | | | | | | | | | | | | The variable `custom_count` is the number of custom fields, so only holds non-negative values, so change the struct member type from int to size_t. Change-Id: Ic35aafefc870092298523ba2e10adf4fcb687a01 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60790 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/ipmi: Use correct unsigned int length modifierPaul Menzel2022-01-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building an image for OCP DeltaLake with `x86_64-linux-gnu-gcc-11` fails with the format warning below as the size of char * differs between 32-bit and 64-bit. CC ramstage/drivers/ipmi/ipmi_fru.o src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_chassis_info_area': src/drivers/ipmi/ipmi_fru.c:192:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=] 192 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for " | ~~^ | | | long int | %d 193 | "chassis custom data array.\n", __func__, 194 | info->custom_count * sizeof(char *)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | unsigned int src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_board_info_area': src/drivers/ipmi/ipmi_fru.c:291:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=] 291 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for " | ~~^ | | | long int | %d 292 | "board custom data array.\n", __func__, 293 | info->custom_count * sizeof(char *)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | unsigned int src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_product_info_area': src/drivers/ipmi/ipmi_fru.c:398:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=] 398 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for " | ~~^ | | | long int | %d 399 | "product custom data array.\n", __func__, 400 | info->custom_count * sizeof(char *)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | unsigned int Fix the mismatches in `read_fru_chassis_info_area()` by using the length modifier `z` for size_t as that is what `size_of` yields to. Change-Id: If0c4266b19d56fa88abc397f305154d473ae1a93 Found-by: gcc (Debian 11.2.0-10) 11.2.0 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/alderlake: Check clkreq overlapKane Chen2022-01-071-1/+8
| | | | | | | | | | | | | | | | | | In some cases, partner may assign same clkreq on more than one devices. This could happen when one device is in baseboard dev tree and another one is in override dev tree. This change adds a clkreq overlap check and shows a warning message TEST=On brya, assigned one clkreq to 2 devices and found the warning message Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/anahera{4es}: Correct WWAN power sequenceWisley Chen2022-01-075-2/+40
| | | | | | | | | | | | | Correct the WWAN power sequence to meet spec BUG=b:213021172 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Iab221fd03c637c82f6ce5c8278d432decf1b30c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/anahera{4es}: Correct SSD power sequenceWisley Chen2022-01-074-2/+36
| | | | | | | | | | | | | M.2 spec describes PERST# should be sequenced after power enable. BUG=b:213021171 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I66345d985f4db4f13b23c0a21c179835908b6574 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/starlabs/merlin: Unify EC and CMOS namesSean Rhodes2022-01-0714-28/+28
| | | | | | | | | | End all CMOS variable with a C and EC variables with an E. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie0fab6b9dcd805f7b8c9bf8f14b0a799d8f396c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/amd/common/block/include/lpc: add comment about RANGE_UNIT valuesFelix Held2022-01-071-1/+1
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22f3485ec81f76af7e0e96b7c1271d5ccf52e701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/lpc/espi_util: move register definitions to header fileFelix Held2022-01-072-48/+56
| | | | | | | | | | | Define the register offsets and bits in a separate header file instead of in the middle of the .c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/espi: use lower case hex digits in definitionsFelix Held2022-01-072-8/+8
| | | | | | | | | | coreboot uses lower case hex digits instead of upper case ones. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0955db7afd101ab522845d5911ff971408e520e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60769 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/lpc/espi_util: handle espi_get_configuration errorFelix Held2022-01-071-1/+2
| | | | | | | | | | | | | | | | | | In espi_wait_channel_ready the return value of espi_get_configuration didn't get checked before. In the case of the espi_send_command call in espi_get_configuration returning CB_ERR, espi_get_configuration didn't write to the local config variable, so if this happens in the first pass of the do-while loop, the following espi_slave_is_channel_ready call would use the uninitialized local config variable as parameter. Fix this by checking the return value of espi_get_configuration. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iff1a0670e17b9d6c6f4daf2ea56badf6c428b8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/brya/var/brask: Change TPM I2C to I2C1Zhuohao Lee2022-01-075-27/+29
| | | | | | | | | | | | | | | The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch moves the TPM I2C setting from the board layer to the baseboard and fixes the TPM I2C bus assignment. BUG=b:211886429 TEST=build pass Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60439 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/herobrine: Fix board idShelley Chen2022-01-061-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board id assignment CL (CB:56642) landed after BOARD_GOOGLE_HEROBRINE has been deprecated to BOARD_GOOGLE_HEROBRINE_REV0 (CB:60284). Fix it to accomodate for the GOOGLE_HEROBRINE_REV0 board updates. BUG=b:211644878 BRANCH=None TEST=built all variants of herobrine to make sure it compiles. For reference: ============= CB:56642: commit 8b63dac06184e56ce40d82d982e983ac79163551 Author: Ravi Kumar Bokka <rbokka@codeaurora.org> Date: Tue Jul 27 19:29:18 2021 +0530 google/herobrine: configure gpio to detect board ID ============= CB:60284: commit 8bdbe23a93008597d99472747ba3415617f8c074 Author: Shelley Chen <shchen@google.com> Date: Tue Dec 21 13:17:33 2021 -0800 mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_REV0 ============= Change-Id: I6dab994e65eadff303eb88a63b8dd81e19694678 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/guybrush/var/dewatt: update USB3 settings for passing SIKenneth Chan2022-01-061-1/+15
| | | | | | | | | | | | | Update tx/rx term control to 3 for passing USB3 port 0/1 SI. b:199468920 TEST= emerge-guybrush coreboot; build and pass USB3 SI. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I637207d7c657f6dd71d70694f9a5fb35f8294b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* mb/google/brya/var/anahera{4es}: Add Chrome OS privacy screen _HIDTim Wawrzynczak2022-01-062-0/+4
| | | | | | | | | | | Similar to commit 0167f5adb (mb/google/redrix: Add _HID for privacy screen device), add the same _HID to the privacy screen device. Change-Id: I58ad538dfaf602e3f4afb98d1a25d52753a15d93 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
* soc/intel/alderlake: Add minimal ACPI support for PEG portsTim Wawrzynczak2022-01-062-0/+22
| | | | | | | | | | | Add minimal Device entries with just an _ADR for each of the PEG ports for P and M chipsets (N does not have any PEG ports). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak2022-01-061-0/+19
| | | | | | | | | | | | | | | | The PMC IPC method used to enable/disable PCIe srcclks uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak2022-01-062-0/+24
| | | | | | | | | | | | | | | | | | The PMC IPC method used to enable/disable PCIe clk sources uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Add new memory supportTony Huang2022-01-063-11/+45
| | | | | | | | | | | | | Do initial memory support for project agah BUG=b:210970640 TEST=FW_NAME=agah emerge-brya coreboot Change-Id: Iaeea12a9dd8110a499b5df4de89dc1f74b88a580 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changedKenneth Chan2022-01-061-11/+3
| | | | | | | | | | | | | | | Due to the CL was merged: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3354766. Update to matched id for audio work normal. 1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2. BUG=b:210542422 TEST=emerge-guybrush coreboot chromeos-bootimage; Download image 14425 and tested audio function. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I542f886fe63205777837d7146169177b043cc5f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* mb/google/brya: Create agah variantTony Huang2022-01-068-0/+46
| | | | | | | | | | | | | | | | | | Create the agah variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:210970640 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_AGAH Change-Id: I6adcf4e8010969cf185513d68bb1b76ea08194c7 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common/gpio: Skip GPP pad lock config if config is not setSubrata Banik2022-01-061-0/+3
| | | | | | | | | | | | | | | | | Don't perform GPP lock configuration if SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS config is not selected. This patch fixes a compilation issue when APL/GLK boards are failing while gpio_lock_pads() function is getting called from IA common gpio block. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I392dc2007dba8169e480f82b58b7f0a1578bb09f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common/gpio: Modify pad_config.pad type from `int` to 'gpio_t'Subrata Banik2022-01-061-1/+1
| | | | | | | | | | | | This patch modifies struct pad_config.pad type from `int` to 'gpio_t' as pad offset inside GPIO community is unsigned type and also to maintain parity with `struct gpio_lock_config.pad` type. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I15da8a1aff2d81805ba6584f5cc7e569faf456e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/intel/common/gpio: Rename struct gpio_lock_config.gpio to .padSubrata Banik2022-01-062-3/+3
| | | | | | | | | | | This patch renames struct gpio_lock_config variable `gpio` to `pad`, to represent the pad offset within the GPIO community. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6bed99c401435c96c9543f99406a934d7141c575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWGSubrata Banik2022-01-061-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the documentation discrepancy of GPIO reset type between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO reset types in Alder Lake as below: - Power Good - (Value 00) - Deep - (Value 01) - Host Reset/PLTRST - (Value 10) - RSMRST for GPD/Reserved for GPP - (Value 11) Hence, created two different reset types for `GPP` and `GPD`. Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET(). BUG=b:213293047 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-06 17:38:15 +0000