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* Documentation: Release notes for the 24.02 release24.02Martin Roth2024-02-201-29/+212
| | | | | | | | | | | | | These will be updated and finalized after the release to capture any final changes, remove "upcoming release", and finalize all stats. Change-Id: Idc224c43f2459faabf91a9ef282bb9eaeba42240 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80617 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier2024-02-193-2/+1
| | | | | | | | | | | | | Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/purism/librem_cnl: Drop selection of USE_LEGACY_8254_TIMERMatt DeVillier2024-02-191-1/+0
| | | | | | | | | | | | | | | | | It's not needed other than for booting w/SeaBIOS, where it is already selected by default, and enabling it with edk2 payload prevents Linux/ Windows from fully entering S0ix. TEST=build/boot purism/librem_cnl (Mini v2), verify Win11/Linux able to enter and exit S0ix properly. Change-Id: I974a82bedc4e06f48ce801f2bc0c29afbd80ffcf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80602 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/starlabs/starbook: Always include the tcss.aslSean Rhodes2024-02-191-2/+0
| | | | | | | | | | | The tcss.asl doesn't just relate to tcss, it is required for core scheduling, so include it for all platforms. Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80485 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Include ADL-N ID 5 0x4618Sean Rhodes2024-02-196-0/+7
| | | | | | | | | | This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/common: Add ADL_N ID 5 0x4618Sean Rhodes2024-02-192-0/+2
| | | | | | | | | | This patch adds ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/liveiso/nixos: Install lm_sensors packageFelix Singer2024-02-191-0/+1
| | | | | | | | Change-Id: I6b027ed39d3ee81878e069142c2d7212f3dc0a6f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber2024-02-1917-57/+20
| | | | | | | | | | | | | | | The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/jasperlake: Drop redundant PcieRpEnableNico Huber2024-02-1919-82/+41
| | | | | | | | | | | | | | | | The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/beadrix: Disable un-used C1 port by daughterboardKevin Yang2024-02-191-0/+18
| | | | | | | | | | | | | | | Probe usb ports by FW_CONFIG setting to disable C1 port on beadrix poin2 new daughterboard without C1 port. BUG=b:316365055 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot Change-Id: I494a922d2b04dcf7bd35680f5d95f8463e225f2d Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/dedede/var/beadrix: Generate SPD ID for supported memory partKevin Yang2024-02-193-2/+5
| | | | | | | | | | | | | | | | Add beadrix supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. CXMT CXDB4CBAM-ML-A BUG=b:321830738 TEST=Use part_id_gen to generate related settings Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* cbfstool: Support 64bit addresses for flat imagesPatrick Georgi2024-02-183-8/+8
| | | | | | | | | | | SELF has the fields wired up for 64bit, but adding flat images cuts the upper half. Change-Id: I3b48b8face921e942fb0e01eace791ad3e1669a0 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80576 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/riscv/Makefile.mk: Fix OpenSBI compilationMaximilian Brune2024-02-181-3/+2
| | | | | | | | | | | | | 1. romstage.S should only be included if we have a separate romstage 2. FW_JUMP and FW_DYNAMIC are opposing options and we only support FW_DYNAMIC Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic14fa77d2f223664b9faba048b759e03efffcde8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79952 Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/crossgcc/buildgcc: Compile RISC-V GCC with medanyMaximilian Brune2024-02-181-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | currently the HiFive Unmatched mainboard produces the following error: ``` util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a (_clzsi2.o): in function `__clzdi2': util/crossgcc/gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in .rodata section in util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/ rv64imafdc/lp64d/libgcc.a(_clz.o) ``` This is due to the fact that the libgcc.a library is compiled with the medlow code model but the mainboards are compiled with the medany code model. Changing the code model of the GCC libraries to the medany code model fixes the issue. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80139 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp/spr: Don't leak memoryPatrick Rudolph2024-02-183-10/+10
| | | | | | | | | | | | | | | | | Only call fill_pds() once to prevent leaking memory. Previously it was called for every active stack on every socket. Only call dump_pds() once to prevent spamming the console with the same information. Drop the return value since it's always returning success. Change-Id: Ifa9609e9da086dc9731556014ea9b320b270d776 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/xeon_sp/uncore: Don't print uninitialized memoryPatrick Rudolph2024-02-181-0/+8
| | | | | | | | | | | | | | | | The struct map_entry has two zero'd entries due to the ifdef being used. Do not read those entries and do not print those entries. Fixes a NULL string being printed along as the vendor and device ID of the PCI device. Change-Id: Id87ced76af552c0d064538f8140d1b78724fb833 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80546 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/cbfstool/linux_trampoline: Support more e820 entriesPatrick Rudolph2024-02-182-21/+36
| | | | | | | | | | | | | | | | | | | | Since linux commit f9ba70535dc12d9eb57d466a2ecd749e16eca866 "[PATCH] Increase number of e820 entries hard limit from 32 to 128" made in 2005 the number of e820 entries passed from the bootloader is 128. Use the boot protocol version to check for support of 128 entries and use them if necessary. Tested on IBM/SBP1: Fixes booting a Linux payload when more than 32 entries are present in the memory table, which can easily happen on a 4 socket platform. Change-Id: Iec0a832fff091b6c3ae7050ef63e743a30618f25 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/purism_librem_cnl/var/*: Drop redundant entries in overridetreesMatt DeVillier2024-02-182-40/+0
| | | | | | | | | | | | | | | | | Now that the baseboard uses chipset devicetree references, remove all references whose value is identical to the chipset devicetree default or the baseboard default, since they are pointless clutter. TEST=build/boot purism/librem_cnl (Mini v2), verify output of lspci and lsusb unchanged before and after patch. Change-Id: I12498e7261dafd7ee59fe79926532399392d1b09 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80600 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/purism/librem_cnl: Drop devicetree entries identical to chipset.cbMatt DeVillier2024-02-181-49/+8
| | | | | | | | | | | | | | | Now that the board uses chipset devicetree references, remove all references whose value is identical to the chipset devicetree default, since they are pointless clutter. TEST=build/boot purism/librem_cnl (Mini v2), run lspci and verify output unchanged before and after patch. Change-Id: I6c656d227962548cebde61f1d82333837adbbf56 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80599 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/mtl: Skip RW CBFS ucode update if RO is lockedSubrata Banik2024-02-181-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch eliminates coreboot from loading microcode from RW CBFS (when the RO descriptor is locked, which indicates a fixed RO image) because the kernel can already patch the microcode on BSPs and APs while booting to OS. This may be a chance to lower the burden on the AP FW side because patching microcode on in-field devices is subject to firmware updates, which are rarely published and, if required, must go through the firmware qualification testing procedure (which is costly, unlike kernel updates for ucode updates). 1. The FIT loads the necessary microcode from the RO during reset. 2. Reloading microcode from RW CBFS impacts boot time (~60ms, core-dependent). 3. The kernel can still load microcode updates. ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is sufficient for initial boot, and the kernel can apply updates later. BUG=none TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode loading when RO is locked. Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
* soc/intel/jasperlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier2024-02-183-2/+1
| | | | | | | | | | | | | Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I8ebb915fbc21f82e39304473b0fcaa620559b5d5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80558 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/tglrvp: Drop selection of SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier2024-02-181-1/+0
| | | | | | | | | | | | | It's already selected at the SoC level, so selecting at the board level is redundant. Change-Id: Ifbe7f88858b9e5e8e5185dbff5853186fd3c66cb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80557 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/common/block/dtt: Add ACPI stub for TCPU deviceMatt DeVillier2024-02-181-0/+25
| | | | | | | | | | | | | | | | | | | | Add an ACPI stub containing the TCPU device in proper scope, along with the device status, on boards not using the DPTF driver, so that there exists an ACPI device to be referenced from the PEPD LPI constraint list. Adding the stub fixes an AE_NOT_FOUND ACPI error under Linux for _SB.PCI0.TCPU on boards with the SA thermal device enabled but which do not use the Intel DPTF driver. TEST=build/boot Linux,Win11 on purism/librem_cnl (Librem Mini v2). Change-Id: I926d0461e5e0dfaf606102575c2be555a6bfb695 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/alderlake/acpi: Drop ACPI stub for SATA deviceMatt DeVillier2024-02-182-10/+0
| | | | | | | | | | | This is now generated by acpigen in the common/block/sata module. Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/common/block/sata: Fix scope for SATA ACPI deviceMatt DeVillier2024-02-181-1/+1
| | | | | | | | | | | | | | | | | | | | | acpi_device_path() includes the device name, so we end up with: Scope (\_SB.PCI0.SATA) { Device (SATA) { ... Fix this by using acpi_device_scope() instead. TEST=build/boot purism librem_cml (Mini v2), dump ACPI and verify SATA device scope correct. Change-Id: Ibbc8890d93b22f0ecba4b3a9b0531994574b3d55 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80554 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/*: Add SPDX headers for cmos.default filesMartin Roth2024-02-1894-0/+188
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* soc: Add SPDX license headers to Kconfig filesMartin Roth2024-02-18122-0/+241
| | | | | | | | | | Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/samsung to mb/up: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1880-0/+152
| | | | | | | | Change-Id: Ied455ff29b151fb5f4bca26a189b1d4104d8cede Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/opencellular to mb/roda: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1851-0/+102
| | | | | | | | | Change-Id: Ia2100d26027a7f71739d5445f781b52c517ed966 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80594 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/inventec to mb/ocp: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1871-0/+142
| | | | | | | | Change-Id: Ib1bbf22480783f63fc2d729b94251e755d2f1720 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80593 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth2024-02-18156-0/+311
| | | | | | | | | Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/cavium to mb/foxcomm: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1842-0/+84
| | | | | | | | Change-Id: Ib100a677935cf3309a380952c35e9060e64433cb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/51nb to mb/bytedance: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1859-0/+118
| | | | | | | | | Change-Id: I71dc3dd270b9a61c86b59031f898af37f0fea345 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80590 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec, lib, security, sb: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1824-1/+47
| | | | | | | | Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers: Add SPDX license headers to Kconfig filesMartin Roth2024-02-18100-0/+200
| | | | | | | | Change-Id: Ib27894f0f1e03501583fffb2c759b493d6a7b945 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80588 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch to cpu: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1841-0/+81
| | | | | | | | Change-Id: I7dd7b0b7c5fdb63fe32915b88e69313e3440b64a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80587 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* payloads: Add SPDX headers to KconfigMartin Roth2024-02-1823-0/+46
| | | | | | | | | Change-Id: Iea569fd457b3cd1f4746fbc6a96319eb42733a6b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80586 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* LICENSES: Add LGPL 2.1 licenseMartin Roth2024-02-181-0/+175
| | | | | | | | | | This is used in util/cbfstool/elf.h and lzmadecode. Change-Id: I75e71259f23bee602ffb54b0c51e0e4a9da3f8e5 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* Treewide: Fix incorrect SPDX license stringsMartin Roth2024-02-1845-45/+45
| | | | | | | | | | | These strings didn't match the license names exactly, so update them to match. Change-Id: Ib946eb15ca5fa64cbd6b657350b989b4a4c1b7b7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/prodrive/hermes: Use chipset dt reference namesFelix Singer2024-02-181-41/+41
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I81dd67fd200768942fe355180b75db0746cda8ea Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/google/rex: Do not power on FPMCU in ramstagePatryk Duda2024-02-173-6/+6
| | | | | | | | | | | | | | | | | | | | | When 'reset_gpio' and 'enable_gpio' properties are defined in overridetree.cb, the kernel will power on the FPMCU. If the device was previously enabled the kernel will reset it. To avoid situation in which the FPMCU is powered on and reset later we leave the FPMCU powered off in coreboot and started by the kernel. This is exactly what other boards do (e.g. brya). TEST=Boot the board (e.g. karis) and make sure the FPMCU was booted once (e.g. examine FPMCU console logs) Change-Id: I5df8d9385be2621c02ccee2d36511a4e80ab87d1 Signed-off-by: Patryk Duda <patrykd@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intelblocks/systemagent: Add missing N6005 Jasper Lake SKU to PCI ID listMichał Żygowski2024-02-171-0/+1
| | | | | | | | Change-Id: I3fb4c6cfe24290c34682ff1c3396540465048727 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/jasperlake/bootblock: Report missing Jasper Lake SKUMichał Żygowski2024-02-171-0/+1
| | | | | | | | Change-Id: Ie0d25eca75225ab33e6c15ef5ccb9073151f4148 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/brox: Handle bluetooth enable on devicesAshish Kumar Mishra2024-02-172-6/+10
| | | | | | | | | | | | | | | | | For devices that require CNVi Bluetooth select WIFI_BT_CNVI in FW_CONFIG. Discrete Bluetooth devices need to select WIFI_BT_PCIE. BUG=b:319188820,b:325084796 BRANCH=None TEST=Boot image on SKU1,SKU2 and check BT devices enumerate. Change-Id: Iba008682fcfa7ddc1ec400649c8742c721666f1d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80564 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPICShelley Chen2024-02-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting the EC interrupt GPIO as an APIC is able to solve many problems that we are currently seeing: 1. Routing through the APIC make the IRQ# associated with this pin unavailable to claim for other devices in the kernel. This is causing EC interrupts to not work. 2. Since EC interrupt are not working, we are not able to flash the EC from the DUT. 3. Also, the GPI_INT configuration does not allow us to set the polarity of the GPIO, which means that it is by default set as active high. As a result, we are seeing an excessive number of host command interrupts to the EC. This disappears when we change the configuration to APIC and set the polarity as INVERT. BUG=b:319129926,b:324707182 BRANCH=None TEST=1. After boot up, check if ec_cros_lpcs driver was successfully registered. Look for the following string: "cros_ec_lpcs GOOG0004:00: Chrome EC device registered" 2. Make sure can flash the EC image from the DUT 3. Make sure EC console is not getting continuous stream of host commands. Change-Id: I74bff88d2ddbaf1f4b085c31d582bd66e18c438a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80467 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.corp-partner.google.com>
* soc/intel/mtl: Double the `IgdDvmt50PreAlloc` UPD size to 128MBSubrata Banik2024-02-161-2/+2
| | | | | | | | | | | | | | This patch increases the IgdDvmt50PreAlloc value as per Intel recommendation starting with GFX PEIM 103x. TEST=Able to build and boot google/rex. Change-Id: I236b38a1ac5efbfcd23e373c09204d8a07b97618 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80406 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/common/tcss: Rename tcss_mux_init to disconnect_tcss_devicesSean Rhodes2024-02-151-2/+2
| | | | | | | | | | | | | | Rename tcss_mux_init to disconnect_tcss_devices to make it clear what this function is doing, as it doesn't initialise anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5e43f0cca9d49bc30fc189663490a306efd71584 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79874 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/starlabs/starbook/rpl: Configure PMC muxSean Rhodes2024-02-151-0/+11
| | | | | | | | | | | | | | Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I580b148b036e62fbcab50d1ca2ab1ed021cfed6b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/adl: Configure PMC muxSean Rhodes2024-02-151-0/+11
| | | | | | | | | | | | | | Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I9e49612d7f165a9c9604093535f7b141a4c7048c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79426 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin: Remove ubtc.aslSean Rhodes2024-02-152-52/+0
| | | | | | | | | | Remove the ubtc.asl as it's no longer needed. Change-Id: I8564bb7d9bd94c8303c543c078bc76192539c5f2 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80484 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 21:02:31 +0000