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* IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS2022-01-281-0/+17
| | | | | | | | | | | | | | | | | IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code and issue a message when the build is complete. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Makefile.inc: Don't ignore IASL's "multiple types" warningElyes HAOUAS2022-01-271-8/+0
| | | | | | | | | | | | Intel Lynx Point ASL code is fixed. So don't ignore "Multiple types (Device object requires either a _HID or _ADR, but not both)" warning. Change-Id: Ie9398879a76ad3d36454772a1c23da083af14b59 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Makefile.inc: Add `-fno-pie` to `ADAFLAGS_common`Paul Menzel2022-01-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Building libgfxinit with Debian’s toolchain – latest test with *gnat-11* 11.2.0-13 from Debian sid/unstable – the build fails with the error below. E: Invalid reloc type: 10 E: Unable to create rmodule from 'build/cbfs/fallback/ramstage.debug'. Debian’s toolchain is built without enabling PIE by default. So, explicitly pass `-fno-pie` to `ADAFLAGS_common` to be independent from how the toolchain was built. TEST=*gnat* 11.2.0-13 successfully. builds purism/librem_cnl/variants/librem_mini with libgfxint. With the coreboot toolchain `make BUILD_TIMELESS=1` produces the same `build/coreboot.rom` for `BOARD_PURISM_LIBREM_MINI_V2=y` on top of commit 50251400d2 (sb/intel/common/firmware: Reword me_cleaner warning) with and without the change. Change-Id: I6661937906d95c130c6099f598d61b21e958fd85 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* guybrush: Inject SPDs into APCBRob Barnes2022-01-101-0/+2
| | | | | | | | | | | | | | Inject SPDs into APCB at coreboot build time. BUG=b:209486191 BRANCH=None TEST=Boot guybrush and nipperkin with injected APCB Change-Id: Ib21085855324e0d473dd5e258f35a52bed326901 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* acpi,Makefile: Add preload_acpi_dsdtRaul E Rangel2021-11-291-0/+3
| | | | | | | | | | | | | | | This will allow us to preload the dsdt.aml file. BUG=b:179699789 TEST=Build guybrush | 80 - write tables | 1.564 | 1.08 Δ( -0.48, -0.03%) | | 85 - finalize chips | 15.483 | 13.543 Δ( -1.94, -0.14%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Makefiles: Hide skipping submodule info unless V=1Martin Roth2021-11-221-8/+8
| | | | | | | | | | | | | Currently, git prints out the submodules that are being skipped twice on many builds. This patch hides that output unless the build is set to show it with `make V=1`. This is the normal way of showing the extra information during the build. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7b5c7f1f79dcc88793a9a21f2e92e7accc5de1e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59511 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/lib/prog_loaders: Add preload_ramstageRaul E Rangel2021-11-161-0/+4
| | | | | | | | | | | | | | This will enable preloading ramstage. By preloading the file into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush to OS and see 12ms reduction in boot time. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/cse_serger: Add a new tool for stitching CSE componentsFurquan Shaikh2021-10-191-2/+6
| | | | | | | | | | | | | This change adds a new tool `cse_serger` which can be used to print, dump and stitch together different components for the CSE region. BUG=b:189177186 Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/cse_fpt: Add a new tool for managing Intel CSE FPT binariesFurquan Shaikh2021-10-191-2/+6
| | | | | | | | | | | | | This change adds a new tool `cse_fpt` which can be used to print and dump CSE partitions in Flash Partition Table (FPT) format. BUG=b:189167923 Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Makefile: Add src/soc/* to subdirsFurquan Shaikh2021-10-111-1/+1
| | | | | | | | | | | | | | | | This change adds src/soc/* to subdirs before src/soc/*/* to allow Makefile in src/soc/* to provide any common helpers that will be useful for any src/soc/*/*. This is done to primarily ensure that the helpers are defined before being invoked by the SoC Makefile.inc. This is utilized by Intel CSE stitching mechanism in following changes. BUG=b:189177580 Change-Id: I91579a87016fdc2b9ca2d798b81969c21c18b4a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* build system: Deduplicate symbols in objdumpPatrick Georgi2021-07-231-1/+2
| | | | | | | | | | | | New binutils versions automatically resolve references to debug symbol files and parse their content as well when objdump'ing data. This leads to multiple mentions of symbols, so deduplicate references. Change-Id: I5d597399c515904313ba36d7aab9178bc0dade14 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile.inc: Replace linker flag -nostartfiles with --nmagicIru Cai2021-07-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | While the gcc(1) driver has the `-nostartfiles` option, ld(1), the program the coreboot toolchain uses to link the object files, doesn't have it. In binutils before 2.36, this option is interpreted as `-n -o startfiles`, in which the `-o` option is overridden by a later `-o` option, so only the `-n` option has effect, which is the `--nmagic` long option of ld(1). So the correct linker option in this place is `--nmagic`. It is tested that without `--nmagic`, ld can generate a much bigger x86_64 romstage, so this option is still needed. This error is found when trying to update binutils to 2.36 and later versions, where ld(1) is unable to disambiguate options and reports an error. Change-Id: I27dc2209abdc6fec866716a252736c5cf236a347 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Revert "Makefile.inc: Drop the cbfs master header from non-X86"Julius Werner2021-07-091-2/+9
| | | | | | | | | | | | | | | This reverts commit d109354c0f1d4b155c60701cd42e632213350d72. Reason for revert: Breaks libpayload CBFS code when accessing non-default CBFS. BUG=b:193093750 Change-Id: Id7f47406e6126f19e1fd6bc9d33c8c9d0cb9450d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Makefile.inc: Drop the cbfs master header from non-X86Arthur Heymans2021-07-071-9/+2
| | | | | | | | | | | | | The pointer to the header has a x86 top mmaped address even though the boot medium is not mapped that way. If no pointer is used to find the header FMAP is needed. If FMAP is used anyway there is no need for a cbfs master header. Change-Id: I6d693bdd4ddaf4c9b3cffb4ea9879c761200aca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Makefile.inc: Fix IFITTOOL dependenciesArthur Heymans2021-07-071-2/+2
| | | | | | | | | | | Add IFITTOOL as a dependency where needed and remove where it is unneeded. Change-Id: I88c9fc19cca0c72e80d3218dbcc76b89b04feacf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Makefile.inc: Remove explicit ramstage dependency for coreboot.romArthur Heymans2021-07-071-1/+1
| | | | | | | | | | This is already handled in $(prebuild-files). Change-Id: I648f97198772d30d6d267ab9d6f7fa8d1d5d0e91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* option: Introduce `CMOS_LAYOUT_FILE` Kconfig symbolAngel Pons2021-05-181-2/+2
| | | | | | | | | | | | | | | Mainboards with variants may not always use the same cmos.layout file. Turn the hardcoded path into a Kconfig symbol to allow changing it. Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom and with `USE_OPTION_TABLE` selected, building for the Asus P8H61-M PRO produces an identical coreboot image. Change-Id: I4cc622dcb70855c06cb8a816c34406f8421180df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54366 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Drop unused `cbfs-files-processor-vsa`Angel Pons2021-05-181-10/+0
| | | | | | | | | | | | VSA (Virtual System Architecture) is specific to AMD Geode CPUs, which are no longer supported in current coreboot. Drop this remnant. Change-Id: I28bf61cb953e3352b59aa91059341e4de8f84f23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Makefile,tests: Move cmocka checkout into top level MakefileRaul E Rangel2021-04-301-0/+2
| | | | | | | | | | | | | | cmocka is currently ignoring the UPDATED_SUBMODULES flag. Move the cmocka checkout with the other submodule checkouts. BUG=none TEST=Make sure cmocka is not checked out if UPDATED_SUBMODULES=1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2a1db809368a77d2c0f9c9a796d62555ec476dc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* Makefile.inc: Use `additional-dirs` for $(objcbfs), $(objgenerated)Nico Huber2021-03-271-7/+6
| | | | | | | | | | | | | | | We use `additional-dirs` for a single `mkdir -p` invocation for all directiories. I don't see why these two, $(objcbfs) and $(objgenerated), should be an exception. Fixes clean builds for targets that don't include the phony `coreboot` target, e.g. `make qemu`. Change-Id: I85abaa74cddefd2bd669e2b5c8934352775070fe Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile.inc: Don't compile bare structs with asan-global=1Arthur Heymans2021-03-171-1/+1
| | | | | | | | | | This messes up the bare structs. Change-Id: I5a13bd9f4b11530a6dd5f572059fed851db44757 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile: Do not use GCC specific options with LLVM/clangPaul Menzel2021-02-181-1/+2
| | | | | | | | | | | | | | | | | | Building with LLVM/clang (`COMPILER_LLVM_CLANG=y`), Debian clang version 11.0.1-2 fails due to unknown warning options. error: unknown warning option '-Wlogical-op'; did you mean '-Wlong-long'? [-Werror,-Wunknown-warning-option] error: unknown warning option '-Wduplicated-cond' [-Werror,-Wunknown-warning-option] As these are GCC specific, only add them, when building with GCC (and not scan-build). Fixes: 04e0712f46 ("Treewide: Add some gcc's warning options") Change-Id: I6190c1f3df97fb0be51f8dab7e1f5f2a033f5d86 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile.inc: Don't ignore _HID & _ADR coexisting in Broadwell ASL codeElyes HAOUAS2021-02-121-3/+3
| | | | | | | | | | Issue fixed in commit d152837 so don't allow use of _HID and _ADR at same time. Change-Id: I52beba66230a3542a7039f496b51be0aa4bdcce4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50384 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Avoid --emit-relocs on RISC-VJulius Werner2021-01-221-1/+7
| | | | | | | | | | | | | | | | | | | There seems to be a bug[1] in the GNU linker for the RISC-V architecture triggered by symbols that are more than 2GB offset from the program counter. My next patch is introducing symbols like that and stuck on this problem. The code path that runs into the issue is only taken when passing the --emit-relocs flag, which is really only needed for building rmodules. Since RISC-V platforms don't use any rmodules at the moment, let's disable the flag on RISC-V until the issue can be fixed in the toolchain. [1]: https://sourceware.org/bugzilla/show_bug.cgi?id=27180 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I784a506034325c0ba937589416acaafbf80080e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49449 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi2021-01-151-2/+2
| | | | | | | | | | | They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* build system: Structure and serialize INTERMEDIATEPatrick Georgi2021-01-141-3/+5
| | | | | | | | | | | | | | | | | | | | | | | Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Add coreboot build system supportPatrick Georgi2021-01-121-4/+1
| | | | | | | | | | | | | When building as part of the coreboot build system, use the same mechanism as other tools (cbfstool, amdfwtool, ...) so that abuild builds ifdtool once into sharedutils instead of once per board (while avoiding other race conditions, too). Change-Id: I42c7b43cc0859916174d59cba6b62630e70287fd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/vpd: Add VPD region to default FMAP when selectedMatt DeVillier2021-01-041-0/+10
| | | | | | | | | | | | | | | | | | Currently, use of the VPD driver to read VPD tables from flash requires the use of a custom FMAP with one or more VPD regions. Extend this funtionality to boards using the default FMAP by creating a dedicated VPD region when the driver is selected. Test: build qemu target with CONFIG_VPD selected, verify entry added to build/fmap.fmd. Change-Id: Ie9e3c7cf11a6337a43223a6037632a4d9c84d988 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/superio: trim and move Makefile.inc, instead use wildcard matchesIdwer Vollering2020-12-271-2/+2
| | | | | | | | | Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: If77d59485451c77dcea752bc4fe0dfadba8fec45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile: Add $(xcompile) to specify where to write xcompileRaul E Rangel2020-12-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file was being written to the root src directory. It is the only file being written to src during a normal build, while all others are being written to $(obj). I added a new variable to allow specifying the xcompile path. This allows generating a single file if building multiple boards. I also moved the default location into $(obj) so we don't pollute the src directory by default. I also cleaned up the generation of xcompile by removing the unnecessary eval and NOCOMPILE check. I also left .xcompile in distclean so it cleans up stale files. Since .xcompile is written into $(obj), `make clean` will now remove it. The tegra Makefiles are outside of the normal build process, so I just updated those Makefiles to point to the default xcompile location of a normal build. The what-jenkins-does target had to be updated to support these special targets. We generate an xcompile specifically for these targets and pass it into the Makefile. Ideally we should get these targets added to the main build. BUG=b:112267918 TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does` Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/28101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* arch/arm: Replace .id section with build_info in CBFSKyösti Mälkki2020-12-171-0/+10
| | | | | | | | | | | | | | | For arch/arm[64], the offsets to board identification strings and CONFIG_ROM_SIZE inside .id were never really used; it was only a convenience to have the strings appear near the start of image. Add the same strings in an uncompressed file in CBFS. Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47602 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/lib: Add Kconfig option for SPD cache in FMAPMatt DeVillier2020-12-141-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Remove the CBNT bootblock flagArthur Heymans2020-12-111-11/+0
| | | | | | | | | | | | | At the moment this was only used for aligning the bootblock to 64 bytes. At the moment this automatically done with CONFIG_C_ENV_BOOTBLOCK_SIZE. Change-Id: I0c879119e525b512eebe3f4c5ff9b2f426c6b6ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* Makefile.inc: Fix empty output when processing C struct files in CBFSXi Chen2020-12-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | When passing $(@) to eval command, $(@) is replaced by empty string, Also, the $(@) in cbfs-files-processor-struct is a temporary file name, so we should quote it by an extra '$' or use the arg ($1 or $2) directly. For example: cbfs-files-processor-struct= \ $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \ # ** $(@) is empty string instead of $(2) ** printf " CC+STRIP $(@) \n"; \ # ** $(1) contains the name of source file ** printf " CC+STRIP $(1) \n"; \ ......) Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Id6a66e25d7dfe8fe6410e517593ed22a438d2f82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48201 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile: Allow platform to provide additional params for add cmdFurquan Shaikh2020-12-081-5/+11
| | | | | | | | | | | | | | | | | | This change adds optional CBFSTOOL_ADD_CMD_OPTIONS that can be used by arch/SoC/mainboard Makefiles to supply any additional arguments that need to be passed into cbfstool when using cbfstool add command. This is useful when platform wants to add these parameters depending upon some arch/SoC/mainboard specific configs. Immediate use case is the fast SPI controller on Intel platforms adding arguments for extended window base and size. BUG=b:171534504 Change-Id: I2f48bc3f494d9a5da7e99b530a39d6078b4a881c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47884 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/trace: Remove TRACE supportKyösti Mälkki2020-12-021-3/+0
| | | | | | | | | | | | | | | | | | | | | Looks like the option is generally not compatible with garbage collections. Nothing gets inlined, for example is_smp_boot() no longer evaluates to constant false and thus the symbols from secondary.S would need to be present for the build to pass even if we set SMP=n. Also the addresses of relocatable ramstage are currently not normalised on the logs, so util/genprof would be unable dress those. Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile.inc: Alloc .bss* sections for "struct" file typeYu-Ping Wu2020-12-011-1/+1
| | | | | | | | | | | | | | | | | | When the global variable of a "struct" CBFS file is zero (for example, CB:47696), the binary will appear in the .bss* section in the ELF file (instead of .data). This results in an empty binary file added to CBFS, so that file size check will fail when reading it at runtime. BUG=b:173751635 TEST=emerge-asurada coreboot TEST=Check sdram-lpddr4x-KMDP6001DA-B425-4GB is non-empty in CBFS BRANCH=none Change-Id: Idfd17d10101a948de0eb0522a672afd5c2f83b04 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47903 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Move adding mcu FIT entriesArthur Heymans2020-11-271-35/+4
| | | | | | | | | | | | This can be done using in the INTERMEDIATE target in the proper place. Change-Id: I28a7764205e0510be89c131058ec56861a479699 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46453 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Add CARRIER_DIR to component discoveryMaxim Polyakov2020-11-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea is to split the “mainboard” category into “variants” and “carrierboards”, in the case when we use the COMe module together with the Carrier Board instead of a single monolithic motherboard. Previously, the “variants” category defined the type of motherboard, which has a number of differences from the base one, for example, it differed in the size or type of memory, and in the configuration of the interfaces. Thus, there is no need to create a separate directory in src/mainboard for a board that is similar in configuration to the base board. But for a COMe module, “variants” contains different variants of only this module, and the entire Carrier Board configuration is allocated to a separate category - “carrierboards”, and each of the variants can be used with one of the many boards in “carrierboards”. For example, in the case of the Kontron mAL10 COMe module, variant refers to the COMe-mAL10 or COMe-m4AL10 module type. They differ in the type of memory (DDR3L or DDR4), and maybe they differ in some chips (see more in https://www.kontron.com/products). However, all variants contain the same type of processor/SoC. The "carrierboards" directory can be able contain both the Kontron's Evalution carrier boards (such as Eval Carrier2 T10 and COMe Ref.Carrier-i T10 TNI) and third party vendor backplanes that are compatible with the COMe modules from “variants”. Thus, the src/mainboard/<module-name> directory contains the common configuration code for all variants from src/mainboard/<module-name>/ variants, which can be supplemented/redefined with a configuration from src/mainboard/<module-name>/carrierboard/<vendor-carrierboard-name>. This architectural solution will be able to systematize and simplify understanding of the code structure for COMe modules and will allow vendors to add/maintain their code in a separate directory. This work is also the first step towards to union of all carrierboards into the global category in src/carrierboard on a par with all boards from src/mainboard. The patch takes this into account in the build system and adds CARRIER_DIR component to use the “carrierboards” category, as it has done for VARIANT_DIR. TEST = Build ROM image for Kontron mAL10 COMe module together with T10 TNI carrier board (https://review.coreboot.org/c/coreboot/+/39133). Change-Id: Ic6b2f8994b1293ae6f5bda8c9cc95128ba0abf7a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42609 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Move adding SeaBIOS cbfs config filesArthur Heymans2020-11-161-16/+0
| | | | | | | | | | Using the INTERMEDIATE target this can be done in the proper dir. Change-Id: Ie105231655ef4b49234f0944f638545fe79f07cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sec/intel/cbnt: Stitch in ACMs in the coreboot imageArthur Heymans2020-11-101-0/+12
| | | | | | | | | | Actual support CBnT will be added later on. Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46456 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/qemu: Add `qemu` make targetNico Huber2020-11-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some mechanics to automatically have a `qemu` make target for supported configurations. So with a QEMU target selected in Kconfig, one would ideally only have to run `make qemu` to test things. There are some notable variables that can be set or adapted in `Makefile.inc` files, the make command line or the environment. Primarily for `Makefile.inc` use: QEMU-y the QEMU executable QEMU_CFG-y a QEMU config that sets the available default devices, used to run more comprehensive tests by default, e.g. many more PCI devices For general use: QEMU_ARGS additional command line arguments (default: -serial stdio) QEMU_EXTRA_CFGS additional config files that can add devices QEMU_CFG_ARGS gathers config file related arguments, can be used to override a default config (QEMU_CFG-y) Examples: $ # Run coreboot's default config with additional command line args $ make qemu QEMU_ARGS="-cdrom site-local/grml64-small_2018.12.iso" $ # Force QEMU's built-in config $ make qemu QEMU_CFG_ARGS= Change-Id: I658f86e05df416ae09be6d432f9a80f7f71f9f75 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* sconfig: Split up sconfig-generated static.hTim Wawrzynczak2020-10-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Currently sconfig generates a `static.h` to accompany `static.c`. However, some payloads may decide they would like to consume the FW_CONFIG macros as well. The current state of `static.h` makes this impossible (relying on `device/device.h`). This patch splits up `static.h` into 3 files: `static.h, `static_devices.h`, and `static_fw_config.h`. `static.h` simply includes the other two `.h` files to ensure no changes are needed to other code. `static_devices.h` contains the extern'd definitions of the device names recently introduced to sconfig. `static_fw_config.h` contains the FW_CONFIG_FIELD_* macros only, which makes it easily consumable by a payload which wishes to use FW_CONFIG. Also refactor the generation of all these output files, as the code was getting messy. Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* drivers/intel/usb4: Add driver for USB4 retimer deviceDuncan Laurie2020-10-191-1/+1
| | | | | | | | | | | | | | | | The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn off the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. BUG=b:156957424 Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sconfig: Allow chipset to provide a base devicetreeDuncan Laurie2020-10-091-1/+7
| | | | | | | | | | | | | | | | | | | | | | | This change extends the devicetree override one more layer and allows the chipset to provide the base devicetree. This allows the chipset to assign alias names to devices as well as set default register values. This works for both the baseboard devicetree.cb as well as variant overridetree.cb. chipset.cb: device pci 15.0 alias i2c0 off end devicetree.cb: device ref i2c0 on end BUG=b:156957424 Change-Id: Ia7500a62f6211243b519424ef3834b9e7615e2fd Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
* amdfwtool: Clean up the Makefile of amdfwtoolZheng Bao2020-10-051-5/+1
| | | | | | | | | | | | | Add Makefile.inc to compliant with other tools. Makefile is kept for building amdfwtool by typing make in the folder. Change-Id: I3688d93de4459f5f838955892086b4b9bf30a9b8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* sconfig: Switch to getoptDuncan Laurie2020-09-181-3/+7
| | | | | | | | | | | | | Instead of positional arguments switch sconfig to use getopt and pass the arguments as options in the build system. This will make it easier to add additional options. Change-Id: I431633781e80362e086c000b7108191b5b01aa9d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile.inc: Print warning type ignored by IASLMaxim Polyakov2020-08-311-3/+6
| | | | | | | | | | | | | | | - Use a new variable to store the list of warning types; - print this list when building an image. TEST = build image on Kontron mAL-10 COMe module: IASL 3150 2158 3133 warning types were ignored! IASL build/dsdt.aml disassembled correctly. Change-Id: I46f761612254b400563f8567be9bd61601f23467 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Makefile.inc: Remove redundant warning flagElyes HAOUAS2020-08-171-2/+2
| | | | | | | | | | | | | | '-Wstrict-aliasing' is turned on by '-Wall'. '-Wstrict-aliasing' is only active when -fstrict-aliasing is active, so add it. 'BUILD_TIMELESS=1' on gigabyte/ga-945gcm-s2l gives the same binary. Change-Id: I51eb8241389f13d2659aef0a3b4b376ce9c651cf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44216 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* assert.h: Do not use __FILE__ nor __LINE__ on timeless buildsAngel Pons2020-07-241-0/+4
| | | | | | | | | | | | | | | | | | | When refactoring, one can move code around quite a bit while preserving reproducibility, unless there is an assert-style macro somewhere... As these macros use __FILE__ and __LINE__, just moving them is enough to change the resulting binary, making timeless builds rather useless. To improve reproducibility, do not use __FILE__ nor __LINE__ inside the assert-style macros. Instead, use hardcoded values. Plus, mention that timeless builds lack such information in place of the file name, so that grepping for the printed string directs one towards this commit. And for the immutable line number, we can use 404: line number not found :-) Change-Id: Id42d7121b6864759c042f8e4e438ee77a8ac0b41 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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