coreboot.git - Coreboot firmware sources

	Commit message (Collapse)	Author	Age	Files	Lines
*	drivers/pc80/rtc: Drop CMOS_POST_EXTRA option	Kyösti Mälkki	2020-04-20	1	-1/+0
\| \| \| \| \| \| \| \|	Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
*	arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE	Kyösti Mälkki	2019-12-19	1	-1/+0
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
*	soc/intel/apollolake: Add reset code to postcar stage	Patrick Georgi	2018-10-23	1	-0/+15
	Also add a test case for that, a config taken from chromiumos with some references to binaries dropped that aren't in our blobs repo (eg audio firmware). Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29223 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>