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* libpayload: Remove legacy CBFS APIJulius Werner2024-02-225-280/+0
| | | | | | | | | | | | | | | It's been several years already since we announced the deprecation of the legacy CBFS API for payloads. It's time to remove it completely. Change-Id: I0ed157ac2d1376b8dff4537af9a63731064b45f6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80650 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* libpayload: timer: Revert timer_hz() return type to 64-bitsJulius Werner2024-02-081-1/+1
| | | | | | | | | | | | | | | | | | It seems that reducing the return type of timer_hz() to uint32_t in CB:78888 was a bad idea... some Intel platforms actually use their raw CPU clock for the timestamp counter which can be higher than 4GHz. This patch reverts it back to uint64_t. Also remove the redundant assertion in timer/generic.c since timer_us() itself already does that check. Cq-Depend: chromium:5274555 Change-Id: I471c7de7a28aec5bb965b23525ed579481ac8361 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Yidi Lin <yidilin@google.com>
* libpayload: Switch to commonlib ipchksum() algorithmJulius Werner2024-02-023-41/+2
| | | | | | | | | | | | | This patch moves libpayload over to the commonlib implementation for calculating the IP checksum. Change-Id: Ie8d323ce9f8d946758619761b4b22d54bce222b6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80253 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Yidi Lin <yidilin@google.com>
* libpayload: Add dma_allocator_range()Yi Chou2023-11-211-0/+1
| | | | | | | | | | | | | | | | | | | Some sensitive data may remain DMA buffer, we will want to zero out everything on the DMA buffer before we jump into the kernel to prevent leaking sensitive data into the kernel. To accomplish that, we will need this function to get the range of memory that can be allocated by the dma allocator. BUG=b:248610274 TEST=emerge-cherry libpayload BRANCH=none Signed-off-by: Yi Chou <yich@google.com> Change-Id: I8f3058dfd861ed44f716623967201b8cabe8d166 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* libpayload/libc/time: Fix possible overflow in multiplicationYidi Lin2023-11-071-1/+1
| | | | | | | | | | | | | | | | | | | | The value from raw_read_cntfrq_el0() could be large enough to cause overflow when multiplied by USECS_PER_SEC. To prevent this, both USECS_PER_SEC and hz can be reduced by dividing them by their GCD. This patch also modifies the return type of `timer_hz()` from `uint64_t` to `uint32_t`, assuming that in practice the timestamp counter should never be that fast. BUG=b:307790895 TEST=boot to kernel and check the timestamps from `cbmem` Change-Id: Ia55532490651fcf47128b83a8554751f050bcc89 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78888 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* {commonlib, libpayload}: Add "has_external_display" in coreboot tableSubrata Banik2023-10-041-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new coreboot table entry named "has_external_display" to understand if external display is attached. This information is useful to prevent graceful shutdown by payload when the LID is closed but an external display is present. This piece of the information will be gathered by coreboot and passed into the payload using this new entry aka external_display because payload (i.e., deptcharge) doesn't have any other way to determine if external display is available. BUG=b:299137940 TEST=Able to build and boot google/rex. w/o this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > System is powered off by depthcharge w/ this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > Booted to OS and device is alive/usable Change-Id: I0fa7eee4c5a50371a7a66c6ca1ac2c7d046d010b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77796 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload: Add vboot and reboot utility functionsJakub Czapiga2023-09-182-0/+16
| | | | | | | | | | | | | | | | | | | | | Patch adds: - vboot_fail_and_reboot() for vboot failures handling. - reboot() weak implementation for payloads to implement, used by vboot_fail_and_reboot(). - vboot_recovery_mode_enabled() to check if recovery mode flag is set in vboot context. Implemented for future libcbfs implementation of VBOOT_CBFS_INTEGRATION in libpayload. BUG=b:197114807 TEST=none Change-Id: I53d1955573d54bc56d05f7780c18dcc8ac1fd399 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* libpayload/vboot: Add vboot context initialization and management codeJakub Czapiga2023-09-181-0/+10
| | | | | | | | | | | | | | | | | | | | | | To fully and easily implement fallback/recovery in libcbfs with vboot support the codebase requires access to vboot context. Moving context management to libpayload allows to avoid unnecessary overhead and code complication and still allows payloads to access it in a way it was designed. Access to this codebase will also allow implementation of e.g. vboot_fail_and_reboot() and other helpful utilities used by coreboot and depthcharge. BUG=b:197114807 TEST=make unit-tests TEST=Build and boot on google/ovis4es with CL:4839296 and VBOOT_CBFS_INTEGRATION enabled Change-Id: Id719be7c4f07251201424b7dc6c1125c6b5756d8 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* libpayload/drivers/video: Add cursor movement support in consoleEran Mitrani2023-09-181-0/+1
| | | | | | | | | | | | | | Add support for moving the console cursor horizontally and vertically. BUG=b:300405745 TEST=Tested using firmware shell on Rex. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I585add120b559396bc0e28aa972b0ae2a33f1fa8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77900 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* libpayload: Outsource delay function into own headerThomas Heijligen2023-08-243-49/+60
| | | | | | | | | | | | For libflashrom we need the delay functions but when including the whole libpayload.h it has conflicting symbols. Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload/include/stdarg.h: Add va_copy builtinMaximilian Brune2023-08-171-0/+1
| | | | | | | | | | Add the builtin to copy variadic lists/arguments. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I4507b901bdce052c5d1701fdf825eb8a96a5b55a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77097 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload: Add parsing of SMBIOS addressMaximilian Brune2023-08-171-0/+1
| | | | | | | | Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ie4032048f5f53b25c46f00b3b48eb5f986a5d0b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* payloads/libpayload/include/coreboot_tables: Use C99 flexible arraysElyes Haouas2023-08-011-7/+7
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Icf3da1b0a0666769ae7b5d5f641b85436b324b4c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76851 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload: strings.h: Use builtin __ffs instead of included oneThomas Heijligen2023-03-071-3/+1
| | | | | | | | | Change-Id: Ie4d0b1b19ce6524341449df8bfabc66bff7bd97e Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70118 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* libpayload: Use __func__ instead of old __FUNCTION__Elyes Haouas2023-02-173-4/+4
| | | | | | | | Change-Id: Ic3c22ac101a2ff44f97b2ac3fe3c0a89391718de Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* commonlib/bsd, libpayload: Do not include helpers.h in stddef.hThomas Heijligen2023-02-161-1/+4
| | | | | | | | | | | | `stddef.h` should only provide the definitions defined by ISO or Posix. The included `commonlib/bsd/helpers.h` provide a lot of non standard definitions that may interfere with definitions from the application. Change-Id: Ia71edbc3ffe6694ff4b971decf3a41f915264bc8 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70116 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload/string: add strndup() functionThomas Heijligen2023-02-161-0/+1
| | | | | | | | Change-Id: Ie509e49f21fb537692704ac6527efa09649164e3 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70115 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* coreboot_tables: Drop uart PCI addrArthur Heymans2022-10-261-8/+0
| | | | | | | | | | | | | | | Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cbfs/vboot: Adapt to new vb2_digest APIJulius Werner2022-09-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* x86/cache.c: Implement dcache_*Hsin-Te Yuan2022-09-012-6/+31
| | | | | | | | | | | | | | | | | | | | | | | | A new ChromeOS automated test will be introduced to check the cbmem log of diagnostic boot mode. Because the diagnostic boot does not allow booting into kernel, the test must perform AP reset and then check the cbmem log afterwards. However, the memory content might not be written back to memory (from CPU cache) during AP reset because of the cache snooping mechanism on x86. Hence, some API to flush cache is needed. Implement dcache_* to allow flushing cache proactively in x86. To avoid unnecessary flush, check dma_coherent before calling dcache_* functions, which will be always true in x86. Therefore, this change won't affect the original functionality. BUG=b:190026346 TEST=FW_NAME=primus emerge-brya libpayload Cq-Depend: chromium:3841252 Signed-off-by: Hsin-Te Yuan <yuanhsinte@google.com> Change-Id: I622d8b1cc652cbe477954a900885d12e6494d94d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* libpayload: Add const for dma_coherent argumentYu-Ping Wu2022-08-241-1/+1
| | | | | | | | | | | | | | | | Add the const modifier for the ptr argument of dma_coherent to avoid unnecessary type casting in payloads. BUG=none TEST=emerge-corsola libpayload BRANCH=none Change-Id: Ic4bb1d8318c7e83fd3ab3054aa0333cb27afe588 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Hsin-Te Yuan <yuanhsinte@google.com>
* treewide: Unify Google brandingJon Murphy2022-07-042-2/+2
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* libpayload: Add commonlib/bsd/elog and its dependencyHsuan Ting Chen2022-06-091-0/+1
| | | | | | | | | | | | | | | | Add commonlib/bsd/elog dependency in libpayload. This will allow other payloads (e.g. depthcharge) to implement their own eventlog read and write utilities. Also include commonlib/bsd/elog.c source to libc-srcs. This ensure payloads could utilize commonlib elog helper functions. Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* commonlib: Clean up compiler.hJulius Werner2022-06-071-53/+0
| | | | | | | | | | | | | | | | | | | | | | | This patch contains several minor cleanups related to compiler.h: - Replace __always_unused() (which is a Linux-specific concept that doesn't make sense without also having __maybe_unused(), and had zero uses in the codebase) with __unused() which moves here from helpers.h - Add __underscores__ to the names of all attributes in the compiler attribute shorthand macros. This is necessary to make them work in files where the same name was already used for an identifier (e.g. cbfstool/cbfs.h's `unused` array of file types). - Remove libpayload's own copy of compiler.h and make it directly pull in the commonlib/bsd copy. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I9644da594bb69133843c6b7f12ce50b2e45fd24b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* libpayload/pci: Add support for bus mappingJianjun Wang2022-05-201-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the common APIs to pci_ops.c and IO based operations to pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* coreboot_tables: Add PCIe info to coreboot tableJianjun Wang2022-05-192-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 'lb_fill_pcie' function to pass PCIe information from coreboot to libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the __weak function. ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller for payloads to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
* libpayload: Fix guards in include/{arm,arm64,x86}/arch/barrier.hDavid Hendricks2022-05-163-3/+3
| | | | | | | | | Change-Id: Ib4897c4f5837f7f3173d5062eecb893adbe36964 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_tJianjun Wang2022-04-141-20/+12
| | | | | | | | | | | | | | | Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no longer needed. Also replace 'struct cbuint64' with 'cb_uint64_t' and remove 'cb_unpack64' in libpayload for compatible with lb_uint64_t. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* commonlib/bsd/helpers: Remove redundancy with libpayload definesJakub Czapiga2022-03-303-47/+2
| | | | | | | | | | | | | Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h Remove redundant defines from libpayload.h and libpayloads' standard headers. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload: Parse the ACPI RSDP table entryArthur Heymans2022-03-302-0/+12
| | | | | | | | Change-Id: I583cda63c3f0b58f8d198ed5ecea7c4619c7a897 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* libpayload: Parse DDR Information using coreboot tablesRavi Kumar Bokka2022-03-162-0/+2
| | | | | | | | | | | | BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59193 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/bsd: Remove cb_err_tJulius Werner2022-03-091-1/+1
| | | | | | | | | | | | | | | | | cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* libpayload: Fix legacy CBFS code after recent refactoringJulius Werner2022-01-141-1/+0
| | | | | | | | | | | | | | | | | | | | The goal when adding the new CBFS API in CB:59497 was that the old CBFS code would be left completely untouched and just moved to the side a bit, so that it could continue to work for the payloads that use it until they all have time to transition to the new CBFS API. Unfortunately, between the different iterations of the patch something went wrong with that and the final committed version of cbfs_legacy.c does differ in some parts from the original code, including a changed macro definition that breaks decompression support. This patch restores all the legacy CBFS files to exactly what they used to be (other than the necessary changes in cbfs_core.h to avoid double definition clashes). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic7fd428acb03d3830f66f807cd1d7cdbd652f409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* libpayload/libcbfs: Add unverified_area APIsJakub Czapiga2022-01-121-0/+22
| | | | | | | | | | | This patch introduces equivalents of unverified_area CBFS access functions added to the main coreboot tree in CB:59678 Change-Id: Ibadfd2a5cb6ad037ef1222b0a4301f90a79a127b Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload: Implement new CBFS access APIJakub Czapiga2022-01-104-222/+241
| | | | | | | | | | | | This commit adds new CBFS API, which is based on the one available in the main coreboot source tree. Libpayload implementation supports RO/RW file lookups and file contents verification. Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload/libc/fmap: Implement new FlashMap APIJakub Czapiga2021-12-233-75/+14
| | | | | | | | | | | This patch introduces new FlashMap API, the fmap_locate_area(). It works on cached FlashMap provided in lib_sysinfo.fmap_cache. Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib: Add __fls() (Find Last Set)Jianjun Wang2021-12-131-0/+3
| | | | | | | | | | | | Implement __fls() as an alias for log2(), and remove the duplicate definitions in commonlib/storage/sdhci.c. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* libpayload: Add boot_device_read() functionJakub Czapiga2021-12-101-0/+22
| | | | | | | | | | | | | | | | This patch adds a new way of implementing flash access for libpayload. Until now all reads had to be performed using cbfs_media, which is obsolete. From now on all reads should be performed using boot_device_read(). This patch also provides a default implementation of boot_device_read() for x86 architecture. Change-Id: I1babd2a8414ed9de3ca49903fcb4f036997b5ff3 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parserJakub Czapiga2021-12-032-2/+16
| | | | | | | | | | | | | | | | | | coreboot stores much information in the CBMEM IMD. Until now it was ignored. This patch makes use of these coreboot tables entries. It also removes get_cbmem_addr() function as it is no longer needed. Moreover, the coreboot tables entry CB_TAG_MRC_CACHE does not exist anymore, as it is not created by the code. It was replaced by CBMEM_ID_MRCDATA entry, so MRCDATA should now be accessible through sysinfo structure field. Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* libpayload: Add mock assert support for unit testing purposesJakub Czapiga2021-11-231-0/+13
| | | | | | | | | | | Some unit tests might require catching assert failures. This patch adds an assert() variant depending on __TEST__ define passed to unit tests. Change-Id: I7e4620400f27dbebc57c71bbf2bf9144ca65807f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* tests: Move x86 I/O functions to include/mock/arch/io.hJakub Czapiga2021-11-041-0/+17
| | | | | | | | | | | | Move th x86 I/O functions declarations from tests mocks to the mock architecture io.h. This will make x86 I/O-dependent tests simpler, because the x86_io.h from mocks will not have to be included manually. Change-Id: Ie7f06c992be306d2523f2079bc90adf114b93946 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* libpayload: Add mock architectureJakub Czapiga2021-10-115-0/+108
| | | | | | | | | | | | | | | | | | | | Mock architecture can be used to build libpayload using host compiler. It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs. Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools provided by xcompile. Mock architecture configuration can be used by payloads for testing purposes. Thanks to it, tests can be architecture-independent, and can be executed without requiring compatible Kconfig options, e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide implementation for most architecture-specific functions present in arch/* directories. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.hNick Vaccaro2021-10-041-0/+6
| | | | | | | | | | | | | | | | | | | | Move the locally declared typec_orientation enum from chip.h to coreboot_tables.h. Change enum typec_orientation name to type_c_orientation for consistency with contents of coreboot_tables.h. Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE. BUG=b:149830546 TEST="emerge-volteer coreboot" and make sure it compiles successfully. Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
* coreboot tables: Add type-c port info to coreboot tableNick Vaccaro2021-10-042-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/mmio: Make buffer_to_fifo32() take a const bufferJulius Werner2021-09-201-4/+2
| | | | | | | | | | | | | The input buffer to the buffer_to_fifo family of functions is only read, so it can be a const pointer. (Also, remove the MIPS check in libpayload for these functions... the MIPS architecture has been removed a while ago.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* nvs: Add Chrome OS NVS (CNVS) information to coreboot tablesFurquan Shaikh2021-06-182-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CB:51638 separated Chrome OS NVS from global NVS by allocating it separately in CBMEM. CNVS is used in depthcharge to fill firmware information at boot time. Thus, location of CNVS needs to be shared in coreboot tables for depthcharge to use. This change adds a new coreboot table tag `CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the location of CNVS in CBMEM to payload (depthcharge). Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the end of GNVS instead of the fixed offset 0x1000. DNVS is used on older Intel platforms like baytrail, braswell and broadwell and depthcharge fills this at boot time as well. Since DNVS is no longer used on any new platforms, this information is not passed in coreboot tables. Instead depthcharge is being updated to use statically defined offsets for DNVS. BUG=b:191324611, b:191324611 TEST=Verified that `crossystem fwid` which reads fwid information from CNVS is reported correctly on brya. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* includes: Move *abs() declarations into `stdlib.h`Nico Huber2021-06-182-3/+9
| | | | | | | | Change-Id: Id4df2d3210735bee737353d293450e59cf93bd9a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* includes: Remove dangling doxygen @}Nico Huber2021-06-181-2/+0
| | | | | | | | Change-Id: I05e02f9689c1a6dafb3943657a3db975c2aeacbe Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55592 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* includes: Define `CHAR_BIT` in `limits.h`Nico Huber2021-06-181-0/+2
| | | | | | | | Change-Id: Ib1d80d0c7457f90596ef5cd9d5ad0c4a33c8d473 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* includes: Provide `wchar.h` with `wchar_t` and `wint_t`Nico Huber2021-06-182-0/+18
| | | | | | | | Change-Id: Iacb0e4eaf3f0b6bf843f3bfda5bdfde0f7a98808 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55590 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-25 05:42:45 +0000