| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | arch/riscv/romstage: Start from assembly | Arthur Heymans | 2023-11-23 | 1 | -4/+0 |
| * | src: remove force-included header rules.h from individual files | Martin Roth | 2022-09-06 | 1 | -2/+0 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | src/arch/riscv: Convert to SPDX license header | Patrick Georgi | 2020-03-06 | 1 | -14/+2 |
| * | riscv: add entry assembly file for RAMSTAGE | Xiang Wang | 2018-09-05 | 1 | -1/+3 |
| * | tree: drop last paragraph of GPL copyright header | Patrick Georgi | 2015-10-31 | 1 | -4/+0 |
| * | Remove empty lines at end of file | Elyes HAOUAS | 2015-06-08 | 1 | -1/+0 |
| * | Remove address from GPLv2 headers | Patrick Georgi | 2015-05-21 | 1 | -1/+1 |
| * | New mechanism to define SRAM/memory map with automatic bounds checking | Julius Werner | 2015-04-06 | 1 | -0/+33 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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