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* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* arch/io.h: Separate MMIO and PNP opsKyösti Mälkki2019-03-041-3/+3
* riscv: Add initial support for 32bit boardsPhilipp Hug2019-02-131-1/+1
* riscv: Simplify payload handlingXiang Wang2019-02-022-2/+9
* riscv: add support smp_pause / smp_resumeXiang Wang2018-11-051-0/+33
* src: Add missing include <stdint.h>Elyes HAOUAS2018-10-301-0/+2
* riscv: add physical memory protection (PMP) supportXiang Wang2018-10-111-0/+31
* Move compiler.h to commonlibNico Huber2018-10-082-3/+0
* arch/riscv/include/arch: Don't use device_tElyes HAOUAS2018-09-211-1/+1
* arch/riscv: provide a monotonic timerPhilipp Hug2018-09-141-0/+10
* arch/riscv: add missing endian.h header to io.hPhilipp Hug2018-09-141-0/+1
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-142-7/+10
* riscv: update misaligned memory access exception handlingXiang Wang2018-09-101-6/+5
* riscv: add entry assembly file for RAMSTAGEXiang Wang2018-09-051-1/+3
* riscv: add support to check machine length at runtimeXiang Wang2018-09-051-0/+6
* riscv: add spin lock supportXiang Wang2018-09-041-0/+28
* riscv: separately define stack locations at different stagesXiang Wang2018-09-021-0/+14
* arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner2018-08-071-1/+0
* riscv: add include/arch/smp/ directoryXiang Wang2018-07-122-0/+100
* riscv: add support to check ISA extensionXiang Wang2018-07-111-0/+7
* RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer2018-04-271-1/+0
* arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer2018-04-111-29/+0
* arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer2018-02-201-74/+224
* arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer2018-02-201-0/+21
* arch/riscv: Remove the current SBI implementationJonathan Neuschäfer2017-12-021-25/+0
* Constify struct cpu_device_id instancesJonathan Neuschäfer2017-11-231-1/+1
* src/arch: Fix checkpatch warning: no spaces at the start of a lineMartin Roth2017-07-251-21/+21
* arch/*: Update Kconfig symbol usageMartin Roth2017-07-071-1/+1
* arch: Unify basic cache clearing APIJulius Werner2017-05-301-0/+40
* riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer2017-01-161-11/+0
* riscv: Add support for timer interruptsRonald G. Minnich2016-12-181-0/+6
* RISCV: Clean up the common architectural codeRonald G. Minnich2016-10-241-2/+2
* RISCV: update the encoding.h file.Ronald G. Minnich2016-10-071-73/+344
* src/arch: Improve code formattingElyes HAOUAS2016-09-122-4/+4
* arch/riscv: Implement the SBI againJonathan Neuschäfer2016-08-231-0/+36
* arch/riscv: Update encoding.h and dependent filesJonathan Neuschäfer2016-08-111-735/+819
* arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer2016-08-021-0/+39
* arch/riscv: Enable unaligned load handlingJonathan Neuschäfer2016-07-191-1/+1
* arch/riscv: copy read/write8/16/32 from x86Jonathan Neuschäfer2016-06-121-0/+30
* lib/coreboot_table: use the architecture dependent table sizeAaron Durbin2016-05-021-0/+2
* arch: introduce architecture dependent common variablesAaron Durbin2016-05-021-0/+26
* arches: lib: add main_decl.h for main() declarationAaron Durbin2016-02-111-1/+1
* arch/{arm64,riscv}: remove jmp_to_elf_entry() declarationAaron Durbin2016-02-111-1/+0
* arch: remove stage_exit()Aaron Durbin2016-02-111-1/+0
* arch/riscv: Add missing license headersMartin Roth2016-01-184-1/+65
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-315-20/+0
* riscv-trap-handling: Add functionality, prevent stack corruptionThaminda Edirisooriya2015-09-151-1/+1
* riscv-trap-handling: Add implementation for trap calls in riscvThaminda Edirisooriya2015-09-102-0/+88
* riscv-spike: support for Spike emulation of riscvThaminda Edirisooriya2015-08-092-603/+761
* Remove empty lines at end of fileElyes HAOUAS2015-06-084-5/+0
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