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* riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengthsXiang Wang2019-06-231-1/+1
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* arch/io.h: Separate MMIO and PNP opsKyösti Mälkki2019-03-041-3/+3
* riscv: Add initial support for 32bit boardsPhilipp Hug2019-02-133-7/+23
* riscv: Simplify payload handlingXiang Wang2019-02-023-3/+16
* arch/riscv: Define and use SBI_ENOSYSJonathan Neuschäfer2018-12-191-0/+2
* riscv: add support for supervisor binary interface (SBI)Xiang Wang2018-11-052-0/+45
* riscv: add support smp_pause / smp_resumeXiang Wang2018-11-052-1/+50
* src: Add missing include <stdint.h>Elyes HAOUAS2018-10-301-0/+2
* riscv: add physical memory protection (PMP) supportXiang Wang2018-10-111-0/+31
* Move compiler.h to commonlibNico Huber2018-10-082-3/+0
* arch/riscv/include/arch: Don't use device_tElyes HAOUAS2018-09-211-1/+1
* arch/riscv: provide a monotonic timerPhilipp Hug2018-09-141-0/+10
* arch/riscv: add missing endian.h header to io.hPhilipp Hug2018-09-141-0/+1
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-142-7/+10
* riscv: update misaligned memory access exception handlingXiang Wang2018-09-101-6/+5
* riscv: update mtime initializationXiang Wang2018-09-101-0/+3
* riscv: add entry assembly file for RAMSTAGEXiang Wang2018-09-051-1/+3
* riscv: add support to check machine length at runtimeXiang Wang2018-09-051-0/+6
* riscv: add spin lock supportXiang Wang2018-09-041-0/+28
* riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang2018-09-041-3/+16
* riscv: separately define stack locations at different stagesXiang Wang2018-09-021-0/+14
* riscv: update the definition of intptr_t/uintptr_tXiang Wang2018-08-301-2/+2
* arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner2018-08-071-1/+0
* riscv: fix issues (timestrap & PRIu64)Xiang Wang2018-07-311-0/+3
* riscv: add include/arch/smp/ directoryXiang Wang2018-07-123-29/+61
* riscv: add support to check ISA extensionXiang Wang2018-07-111-0/+7
* riscv: use __riscv_atomic to check support A extensionXiang Wang2018-07-061-1/+1
* RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer2018-04-271-1/+0
* arch/riscv: Store mprv bit in size_tJonathan Neuschäfer2018-04-261-2/+2
* arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer2018-04-111-29/+0
* arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer2018-02-201-74/+224
* arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer2018-02-201-0/+21
* arch/riscv: Don't set up virtual memoryJonathan Neuschäfer2018-02-201-25/+0
* arch/riscv: Remove the current SBI implementationJonathan Neuschäfer2017-12-022-53/+0
* Constify struct cpu_device_id instancesJonathan Neuschäfer2017-11-231-1/+1
* arch/riscv: mprv_read_*: Mark result as earlyclobberJonathan Neuschäfer2017-11-071-1/+1
* arch/riscv: Fix return type of mprv_read_u64Jonathan Neuschäfer2017-11-071-1/+1
* arch/riscv: Document mprv_{read,write}_* functionsJonathan Neuschäfer2017-09-271-0/+11
* src/arch: Fix checkpatch warning: no spaces at the start of a lineMartin Roth2017-07-254-42/+42
* arch/*: Update Kconfig symbol usageMartin Roth2017-07-071-1/+1
* arch: Unify basic cache clearing APIJulius Werner2017-05-301-0/+40
* riscv: Suppress invalid coverity errorsMartin Roth2017-02-201-0/+1
* riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer2017-01-162-11/+14
* riscv: get SBI calls to workRonald G. Minnich2017-01-161-16/+26
* riscv: Add support for timer interruptsRonald G. Minnich2016-12-181-0/+6
* riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer2016-11-071-2/+2
* RISCV: Clean up the common architectural codeRonald G. Minnich2016-10-242-13/+4
* riscv: Clean up {qemu,spike}_utilJonathan Neuschäfer2016-10-151-17/+1
* RISCV: update the encoding.h file.Ronald G. Minnich2016-10-071-73/+344
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