coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths	Xiang Wang	2019-06-23	1	-1/+1
*	riscv: Add initial support for 32bit boards	Philipp Hug	2019-02-13	1	-2/+9
*	riscv: Simplify payload handling	Xiang Wang	2019-02-02	1	-1/+7
*	riscv: add support smp_pause / smp_resume	Xiang Wang	2018-11-05	1	-1/+17
*	riscv: update mtime initialization	Xiang Wang	2018-09-10	1	-0/+3
*	riscv: add include/arch/smp/ directory	Xiang Wang	2018-07-12	1	-1/+0
*	arch/riscv: Remove the current SBI implementation	Jonathan Neuschäfer	2017-12-02	1	-28/+0
*	src/arch: Fix checkpatch warning: no spaces at the start of a line	Martin Roth	2017-07-25	1	-3/+3
*	riscv: Suppress invalid coverity errors	Martin Roth	2017-02-20	1	-0/+1
*	riscv: Move mcall numbers to mcall.h, adjust their names	Jonathan Neuschäfer	2017-01-16	1	-0/+14
*	riscv: get SBI calls to work	Ronald G. Minnich	2017-01-16	1	-16/+26
*	riscv: Unify SBI call implementations under arch/riscv/	Jonathan Neuschäfer	2016-11-07	1	-0/+70