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path: root/src/cpu/intel/haswell/haswell.h
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* cpu: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas2022-11-081-1/+1
* soc/intel/broadwell: Use Haswell CPU headersAngel Pons2021-01-241-0/+7
* cpu/intel/haswell: Add fast ramp voltage for BroadwellAngel Pons2021-01-241-0/+6
* cpu/intel/haswell: Enable timed MWAIT if supportedAngel Pons2021-01-221-0/+1
* cpu/intel/haswell: Clean up CPUID definitionsAngel Pons2021-01-211-13/+26
* cpu/intel/haswell/acpi.c: Use C-state enum definitionsAngel Pons2021-01-151-0/+21
* cpu/intel/haswell/haswell.h: Align with BroadwellAngel Pons2021-01-101-41/+29
* cpu/intel/haswell: Do not determine CPU type at runtimeAngel Pons2021-01-101-3/+4
* cpu/intel/haswell: Rename `HASWELL_BCLK` to `CPU_BCLK`Angel Pons2021-01-071-1/+1
* cpu/intel/haswell: Move smmrelocate.c MSR definitions to headerAngel Pons2020-11-031-0/+20
* {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons2020-10-311-1/+1
* {cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner2020-10-241-1/+0
* haswell: relocate `romstage_common` to northbridgeAngel Pons2020-07-081-10/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-041-13/+2
* src: Remove unused 'include <arch/cpu.h>'Elyes HAOUAS2019-12-191-1/+1
* intel/haswell: Remove some __PRE_RAM__ useKyösti Mälkki2019-09-131-11/+1
* AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth2019-09-101-2/+0
* cpu/intel: Enter romstage without BISTKyösti Mälkki2019-08-181-1/+0
* soc/intel: Rename some SMM support functionsKyösti Mälkki2019-08-151-7/+0
* cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki2019-08-151-2/+0
* intel/haswell: Move stage_cache support functionKyösti Mälkki2019-08-031-8/+2
* cpu/x86: Move smm_lock() prototypeKyösti Mälkki2019-07-131-0/+1
* cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35Elyes HAOUAS2019-06-211-1/+1
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-111-13/+0
* src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS2018-10-051-1/+1
* cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans2018-06-141-17/+0
* cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans2018-06-051-3/+0
* cpu/intel/haswell: Fix undefined behaviorRyan Salsamendi2017-07-061-1/+1
* cpu/intel: Fix the spacing issuesLee Leahy2017-03-161-2/+2
* cpu/intel: Indent with tabsLee Leahy2017-03-161-2/+2
* intel/haswell: Add asmlinkage for romstage_after_car()Kyösti Mälkki2016-07-231-1/+1
* cpu/intel/haswell: convert to using common MP and SMM initAaron Durbin2016-05-061-3/+5
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-2/+1
* haswell: move to mp_init libraryAaron Durbin2014-05-051-8/+1
* coreboot: config to cache ramstage outside CBMEMAaron Durbin2014-01-301-16/+0
* src/cpu: Fix spelling of MTTR to MTRRPaul Menzel2014-01-261-8/+8
* haswell: Export functions for CPU family+model and steppingDuncan Laurie2013-12-121-1/+18
* haswell: VR controller configurationAaron Durbin2013-12-071-0/+2
* haswell: Misc power management setup and fixesDuncan Laurie2013-12-071-0/+1
* slippy/falco/peppy: Fix SPD GPIO initialization.Aaron Durbin2013-12-011-0/+1
* haswell: Configure PCH power sharing for ULTDuncan Laurie2013-11-241-0/+2
* haswell: calibrate 24MHz clock against BCLKAaron Durbin2013-11-241-0/+19
* haswell: configure c-statesAaron Durbin2013-11-241-8/+6
* cpu: Fix spellingMartin Roth2013-07-111-1/+1
* haswell: allow for disabled hyperthreadingAaron Durbin2013-06-031-0/+3
* Drop prototype guarding for romccStefan Reinauer2013-05-101-1/+1
* haswell: use asmlinkage for assembly-called funcsAaron Durbin2013-05-071-1/+3
* haswell: implement ramstage caching in SMM regionAaron Durbin2013-03-211-0/+17
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