coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	arch to cpu: Add SPDX license headers to Kconfig files	Martin Roth	2024-02-18	1	-0/+2
*	src: Introduce `ARCH_ALL_STAGES_X86`	Angel Pons	2021-07-02	1	-1/+0
*	src: Move `select ARCH_X86` to platforms	Angel Pons	2021-06-30	1	-0/+1
*	arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`	Angel Pons	2020-09-26	1	-4/+1
*	cpu,soc/intel: Drop select SMP	Kyösti Mälkki	2020-07-26	1	-1/+0
*	Drop superfluous C_ENVIRONMENT_BOOTBLOCK checks	Arthur Heymans	2019-11-25	1	-1/+1
*	cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE	Kyösti Mälkki	2019-11-03	1	-1/+0
*	cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.	Arthur Heymans	2019-11-02	1	-0/+1
*	intel/cpu: Switch older models to TSC_MONOTONIC_TIMER	Kyösti Mälkki	2019-09-24	1	-1/+3
*	cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASE	Kyösti Mälkki	2019-09-19	1	-0/+1
*	cpu/intel/model_1067x: Select UDELAY_LAPIC	Arthur Heymans	2017-10-29	1	-1/+1
*	cpu/intel/common: Add/Use common function to set virtualization	Matt DeVillier	2016-12-27	1	-0/+1
*	Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/Kconfig	Arthur Heymans	2016-11-09	1	-0/+1
*	vboot2: add verstage	Stefan Reinauer	2015-01-27	1	-0/+1
*	Introduce stage-specific architecture for coreboot	Furquan Shaikh	2014-05-06	1	-1/+3
*	Move ARCH_* from board/Kconfig to cpu or soc Kconfig.	Furquan Shaikh	2014-05-03	1	-0/+1
*	cpu/intel: Make all Intel CPUs load microcode from CBFS	Alexandru Gagniuc	2014-01-16	1	-0/+1
*	Synchronize rdtsc instructions	Stefan Reinauer	2012-08-09	1	-0/+1
*	Intel cpus: apply un-written naming rules	Kyösti Mälkki	2012-02-10	1	-1/+1
*	HAVE_MOVNTI really means SSE2. Also add sfence in the MOVNTI case.	Stefan Reinauer	2010-02-25	1	-1/+1
*	Remove default n statements to simplify .config and ldoptions files.	Myles Watson	2009-10-09	1	-1/+0
*	Various fixes to Kconfig: All kconfig-boards should have a	Patrick Georgi	2009-10-06	1	-1/+1
*	some progress on kconfig:	Patrick Georgi	2009-09-25	1	-0/+5