summaryrefslogtreecommitdiffstats
path: root/src/cpu/intel/model_6fx
Commit message (Expand)AuthorAgeFilesLines
* Drop superfluous C_ENVIRONMENT_BOOTBLOCK checksArthur Heymans2019-11-251-1/+1
* cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki2019-11-031-1/+0
* cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.Arthur Heymans2019-11-021-0/+1
* intel/cpu: Switch older models to TSC_MONOTONIC_TIMERKyösti Mälkki2019-09-241-1/+3
* cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASEKyösti Mälkki2019-09-191-0/+1
* AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth2019-09-101-2/+0
* cpu/intel: Drop SMM_TSEG conditionalKyösti Mälkki2019-07-091-1/+1
* Use 3rdparty/intel-microcodeArthur Heymans2019-07-011-1/+1
* src: Use 'include <string.h>' when appropriateElyes HAOUAS2019-03-201-1/+0
* cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRRArthur Heymans2019-01-241-3/+0
* nb/intel/x4x: Use parallel MP initArthur Heymans2019-01-231-17/+0
* nb/intel/gm45: Use parallel MP initArthur Heymans2019-01-232-4/+9
* cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()Matt DeVillier2018-12-201-1/+1
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-111-1/+0
* src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS2018-10-051-2/+2
* nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans2018-07-301-0/+1
* intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)Elyes HAOUAS2017-11-301-1/+1
* Constify struct cpu_device_id instancesJonathan Neuschäfer2017-11-231-1/+1
* cpu/intel: Wrap lines at 80 columnsLee Leahy2017-03-161-2/+4
* cpu/intel: Fix the spacing issuesLee Leahy2017-03-161-2/+2
* cpu/intel: Indent with tabsLee Leahy2017-03-161-1/+1
* cpu/intel/model_6{e,f}x: Unify init filesPaul Menzel2017-03-091-6/+5
* cpu/intel/model_6fx: Add Conroe-L to cpu_device_id listArthur Heymans2017-01-101-0/+1
* cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier2016-12-273-34/+5
* src/cpu: Improve code formattingElyes HAOUAS2016-09-041-1/+1
* src/cpu: Capitalize CPU, APIC and IOAPIC typo fixElyes HAOUAS2016-08-231-1/+1
* src/cpu: Capitalize CPUElyes HAOUAS2016-07-311-2/+2
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc2015-09-302-4/+1
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-2/+1
* 3rdparty: move to 3rdparty/blobsPatrick Georgi2015-05-051-1/+1
* 3rdparty: Move to blobsPatrick Georgi2015-05-051-1/+1
* cpu/intel: (non-FSP) Remove microcode updates from treeAlexandru Gagniuc2015-02-2818-5238/+0
* cpu/intel (non-FSP): Use microcode from blobs repositoryAlexandru Gagniuc2015-02-281-18/+1
* vboot2: add verstageStefan Reinauer2015-01-271-0/+1
* {arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan2014-10-271-1/+1
* cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-081-1/+0
* Introduce stage-specific architecture for corebootFurquan Shaikh2014-05-061-1/+3
* Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh2014-05-031-0/+1
* PCI: Drop includes under cpuKyösti Mälkki2014-02-121-1/+0
* cpu/intel: Remove dummy terminators from microcode blobsAlexandru Gagniuc2014-01-161-6/+0
* cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc2014-01-164-28/+30
* usbdebug: Drop old includesKyösti Mälkki2013-07-111-1/+0
* usbdebug: Drop temporary disables of log outputKyösti Mälkki2013-06-141-15/+0
* Intel: Update CPU microcode for 6fx CPUsStefan Reinauer2013-03-2136-4964/+5257
* speedstep: Deduplicate some MSR identifiersPatrick Georgi2013-02-091-8/+4
* Get rid of drivers classPatrick Georgi2012-11-271-1/+1
* Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber2012-11-011-1/+0
* Synchronize rdtsc instructionsStefan Reinauer2012-08-091-0/+1
* Revert "Use broadcast SIPI to startup siblings"Sven Schnelle2012-07-312-0/+4
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 21:33:42 +0000