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path: root/src/cpu/intel/slot_1/Kconfig
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* x86: Add pre-memory stages CBFS cache scratchpad supportJeremy Compostella2023-10-201-0/+3
* cpu: Get rid of CPU_SPECIFIC_OPTIONSElyes Haouas2023-08-041-5/+2
* cpu/intel/*/Kconfig: move selection of CPU_X86_CACHE_HELPERFelix Held2021-10-261-1/+0
* cpu/x86: Introduce `CPU_X86_CACHE_HELPER`Felix Held2021-10-261-0/+1
* cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OSTim Wawrzynczak2021-04-291-0/+1
* treewide [Kconfig]: Remove useless commentElyes HAOUAS2021-02-021-1/+1
* arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki2021-01-281-2/+1
* cpu/intel/slot_1: Select 16KiB bootblock if console is enabledKeith Hui2020-06-041-0/+1
* src: Remove leading blank lines from SPDX headerElyes HAOUAS2020-05-181-2/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-091-9/+1
* cpu/intel/slot_1: Cache romstage XIP executionArthur Heymans2020-03-031-0/+1
* cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-251-1/+8
* Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans2019-11-251-0/+1
* intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMERKyösti Mälkki2019-11-051-1/+2
* cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki2019-11-031-0/+1
* AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth2019-09-101-2/+0
* arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki2019-07-091-0/+1
* cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki2019-07-091-0/+1
* cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki2018-06-171-1/+1
* cpu/intel/slot_1: Increase CAR size to 8KiBKeith Hui2017-09-121-2/+2
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-1/+1
* intel CAR: Fix DCACHE_RAM_BASE for old socketsKyösti Mälkki2014-12-301-0/+4
* Drop redundant select CACHE_AS_RAMKyösti Mälkki2014-07-051-1/+0
* cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc2014-01-161-1/+11
* GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel2013-03-011-1/+1
* Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.Uwe Hermann2010-10-151-5/+0
* Convert all Intel 440BX boards to Cache-as-RAM (CAR).Uwe Hermann2010-10-061-0/+1
* license header fixes Nils Jacobs2010-05-141-2/+1
* Add proper Slot 1 CPU support code/infrastructure.Keith Hui2010-03-051-0/+33
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