coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	nb/intel/pineview: Use cbfs mcache	Arthur Heymans	2022-04-27	1	-1/+1
*	cpu/intel/socket_FCBGA559: Drop 'select SSE'	Elyes HAOUAS	2022-01-27	1	-1/+0
*	cpu/x86: Introduce and use `CPU_X86_LAPIC`	Felix Held	2021-10-26	1	-1/+0
*	cpu/intel/*/Kconfig: move selection of CPU_X86_CACHE_HELPER	Felix Held	2021-10-26	1	-1/+0
*	cpu/x86: Introduce `CPU_X86_CACHE_HELPER`	Felix Held	2021-10-26	2	-1/+1
*	cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCs	Felix Held	2021-10-25	1	-1/+0
*	cpu/x86/tsc: Deduplicate Makefile logic	Angel Pons	2021-09-08	1	-1/+0
*	cpu/intel/hyperthreading: Build only for selected models	Kyösti Mälkki	2021-06-07	1	-1/+0
*	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	Arthur Heymans	2021-05-18	1	-1/+0
*	pineview boards: Factor out MAX_CPUS	Angel Pons	2020-06-15	1	-0/+4
*	arch/x86: Remove NO_FIXED_XIP_ROM_SIZE	Kyösti Mälkki	2020-06-15	1	-1/+0
*	nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK	Arthur Heymans	2019-05-25	2	-1/+10
*	cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE	Arthur Heymans	2019-04-25	1	-0/+1
*	cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup	Arthur Heymans	2019-01-15	2	-2/+5
*	nb/intel/pineview: Switch to POSTCAR_STAGE	Arthur Heymans	2018-06-05	1	-4/+1
*	cpu/intel/car: Prepare for some POSTCAR_STAGE support	Kyösti Mälkki	2018-06-02	1	-0/+5
*	cpu/intel/pineview: Include speedstep	Arthur Heymans	2017-06-28	1	-0/+1
*	intel cache-as-ram: Move DCACHE_RAM_BASE	Kyösti Mälkki	2016-12-18	1	-1/+1
*	intel model_106cx: Include CAR from socket directory	Kyösti Mälkki	2016-07-22	1	-0/+3
*	cpu/intel/socket_FCBGA559: Add new socket for Atom D5xx	Damien Zammit	2015-11-24	2	-0/+28