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* intel car: Use MTRR WRPROT type for XIP cacheKyösti Mälkki2016-07-262-2/+2
* intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki2016-07-261-4/+7
* intel/haswell: Remove useless MTRR clearKyösti Mälkki2016-07-231-8/+0
* intel/haswell post-car: Minor fix on MTRR settingKyösti Mälkki2016-07-231-2/+2
* intel/haswell: Add asmlinkage for romstage_after_car()Kyösti Mälkki2016-07-232-2/+2
* intel car: Unify postcodesKyösti Mälkki2016-07-225-27/+22
* intel car: Unify whitespace and comment fixesKyösti Mälkki2016-07-225-16/+15
* intel car: Remove guard on XIP_ROM_SIZEKyösti Mälkki2016-07-223-7/+0
* intel model_106cx: Include CAR from socket directoryKyösti Mälkki2016-07-223-2/+6
* intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki2016-07-101-15/+1
* intel/haswell: No need for ACPI S3 resume backupKyösti Mälkki2016-06-291-7/+0
* intel romstage: Use run_ramstage()Kyösti Mälkki2016-06-291-2/+2
* ACPI S3: Add common recovery codeKyösti Mälkki2016-06-221-17/+2
* Ignore RAMTOP for MTRRsKyösti Mälkki2016-06-225-6/+6
* intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-222-2/+9
* intel/model_2065x: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-222-2/+9
* intel cache-as-ram: Fix comment about MTRRsKyösti Mälkki2016-06-223-6/+6
* intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-215-2/+12
* intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-214-3/+11
* intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki2016-06-216-2/+13
* intel: Fix romstage main() with asmlinkageKyösti Mälkki2016-06-181-0/+7
* intel/cache_as_ram_ht.inc: Fix includeKyösti Mälkki2016-06-182-2/+2
* intel cache_as_ram: Fix typo in commentKyösti Mälkki2016-06-181-1/+1
* intel/model_206ax: Move platform specific definesKyösti Mälkki2016-06-171-1/+1
* Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki2016-06-172-0/+2
* Fix some cbmem.h includesKyösti Mälkki2016-06-173-3/+1
* {cpu,soc}/intel: remove unused smm_init() functionAaron Durbin2016-05-061-9/+0
* cpu/intel/haswell: convert to using common MP and SMM initAaron Durbin2016-05-063-197/+88
* cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin2016-05-041-1/+0
* cpu/x86/mp_init: remove unused callback argumentsAaron Durbin2016-05-021-6/+6
* northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer2016-03-101-1/+0
* x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin2016-03-084-14/+4
* tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli2016-02-261-1/+1
* CPU/intel: Add missing license headersDamien Roth2016-02-1414-0/+182
* Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko2016-02-121-2/+0
* cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin2016-02-102-4/+5
* Remove #ifdef checks on Kconfig symbolsMartin Roth2015-12-061-4/+0
* fsp_model_406dx: use external microcode .h files for rangeleyMartin Roth2015-12-063-15/+9
* x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit2015-12-021-0/+1
* cpu/intel/socket_FCBGA559: Add new socket for Atom D5xxDamien Zammit2015-11-245-0/+31
* fsp1_0: Remove hardcoded microcode locationsMartin Roth2015-11-201-5/+0
* intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian2015-11-162-1/+5
* intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian2015-11-163-0/+21
* cpu/intel: Add socket BGA1284Marc Jones2015-11-104-0/+20
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-3178-312/+0
* sandybridge: Disable parallel CPU initializationNico Huber2015-10-311-1/+0
* cpu/intel/fsp_model_206ax: Load microcode in corebootMartin Roth2015-10-283-6/+6
* cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel2015-10-231-0/+0
* Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth2015-10-2211-0/+1219
* cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc2015-10-1513-178/+178
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