summaryrefslogtreecommitdiffstats
path: root/src/cpu
Commit message (Expand)AuthorAgeFilesLines
* src: use ARRAY_SIZE where possiblePatrick Georgi2021-02-151-1/+1
* cpu/intel/haswell: Constify ACPI c-state arraysAngel Pons2021-02-141-4/+4
* cpu/intel/haswell: Drop c-state table indirectionAngel Pons2021-02-142-96/+88
* cpu/intel/model_206ax: Drop c-state table indirectionAngel Pons2021-02-142-90/+78
* cpu/intel/model_206ax: Replace `generate_cstate_entries`Angel Pons2021-02-141-37/+15
* cpu/intel/haswell/acpi.c: Correct `get_cores_per_package`Angel Pons2021-02-121-14/+4
* src: Remove unused <arch/cpu.h>Elyes HAOUAS2021-02-114-4/+3
* cpu/intel/microcode: Fix typo in function parameterElyes HAOUAS2021-02-111-1/+1
* mb/emulation/qemu: Fix SMP bootPatrick Rudolph2021-02-041-2/+2
* treewide [Kconfig]: Remove useless commentElyes HAOUAS2021-02-025-5/+5
* cpu/x86/name/name.c: Clean up includesElyes HAOUAS2021-02-011-2/+2
* sb/intel/i82801gx,ix: Drop MPEN from GNVSKyösti Mälkki2021-02-012-0/+5
* cpu/x86/mp_init.c: Print out the microcode revision of APsArthur Heymans2021-02-011-2/+6
* cpu/intel/microcode: Reuse existing function to read MCU revisionArthur Heymans2021-02-011-10/+4
* soc/intel/*: Get rid of custom microcode cachingPatrick Rudolph2021-02-013-14/+7
* cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZEArthur Heymans2021-01-281-1/+1
* cpu/intel/microcode: Add caching layer in intel_microcode_findPatrick Rudolph2021-01-281-1/+6
* cpu/intel/common/fsb.c: Correct code styleFrans Hendriks2021-01-281-1/+0
* cpu/amd/agesa/family15tn/fixme.cFrans Hendriks2021-01-281-7/+7
* arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki2021-01-285-18/+1
* arch/x86: Top-align .init in bootblockKyösti Mälkki2021-01-281-1/+0
* cpu/x86: Rename __protected_start symbolKyösti Mälkki2021-01-282-5/+6
* cpu/x86: Link entry32.incKyösti Mälkki2021-01-283-33/+80
* cpu/x86: Link reset16.incKyösti Mälkki2021-01-282-1/+1
* cpu/x86: Link entry16.incKyösti Mälkki2021-01-283-2/+9
* cpu/intel/common/fsb.c: Add Broadwell CPUID modelsAngel Pons2021-01-261-0/+2
* cpu/x86/smm: Remove unused APMC for C-state and P-stateKyösti Mälkki2021-01-261-6/+0
* cpu/x86/smm: Use common APMC loggingKyösti Mälkki2021-01-252-7/+26
* cpu/intel/model_2065x: Drop configurable TDP copy-pastaAngel Pons2021-01-243-41/+7
* cpu/intel/model_2065x: Drop unused c-state codeAngel Pons2021-01-243-158/+1
* soc/intel/broadwell: Move romstage.c to HaswellAngel Pons2021-01-242-0/+32
* soc/intel/broadwell: Use Haswell CPU headersAngel Pons2021-01-241-0/+7
* cpu/intel/haswell: Add Broadwell CPUIDs and microcodeAngel Pons2021-01-242-0/+8
* cpu/intel/haswell: Set C9/C10 vccminAngel Pons2021-01-241-0/+23
* cpu/intel/haswell: Add fast ramp voltage for BroadwellAngel Pons2021-01-242-2/+11
* cpu/intel/haswell: Enable timed MWAIT if supportedAngel Pons2021-01-222-1/+8
* cpu/intel/haswell: Clean up CPUID definitionsAngel Pons2021-01-212-20/+33
* cpu/intel/haswell: Add s0ix supportAngel Pons2021-01-212-1/+27
* cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZEElyes HAOUAS2021-01-211-1/+1
* cpu/x86/sipi_vector.S: Fix reading MCU revisionArthur Heymans2021-01-191-0/+4
* cpu/x86/smm/smm_module_loaderv2.c: Remove repeated wordElyes HAOUAS2021-01-181-1/+1
* cpu/x86/mtrr/earlymtrr.c: Remove repeated wordElyes HAOUAS2021-01-181-1/+1
* cpu/intel/smm/gen1/smmrelocate.c: Remove repeated wordElyes HAOUAS2021-01-181-1/+1
* build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi2021-01-151-2/+2
* cpu/intel/haswell/acpi.c: Use C-state enum definitionsAngel Pons2021-01-153-27/+27
* cpu/intel/haswell: Factor out ACPI C-state valuesAngel Pons2021-01-152-71/+27
* cpu/intel/*init: Remove obsolete cache enablePatrick Rudolph2021-01-154-12/+0
* cpu/mp_init: Fix microcode lockPatrick Rudolph2021-01-151-2/+2
* cpu/x86/mpinit: Serialize microcode updates for HT threadsPatrick Rudolph2021-01-154-3/+20
* build system: Structure and serialize INTERMEDIATEPatrick Georgi2021-01-141-6/+2
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-28 14:57:28 +0000