summaryrefslogtreecommitdiffstats
path: root/src/include/cpu/intel
Commit message (Expand)AuthorAgeFilesLines
* soc/intel: Add Lunar Lake device IDsAppukuttan V K2024-01-241-0/+1
* src: Remove unnecessary semicolons from the end of macrosMartin Roth2023-11-101-1/+1
* arch/x86: Reduce max phys address size for Intel TME capable SoCsJeremy Compostella2023-09-121-0/+3
* src/*/post_code.h: Change post code prefix to POSTCODEYuchen He2023-08-051-20/+20
* treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski2023-07-121-11/+11
* soc/intel/alderlake: Add support for Raptor Lake S CPUsMax Fritz2023-07-121-0/+4
* soc/intel/meteorlake: Add QS(C0) stepping CPU IDMusse Abdullahi2023-06-291-0/+1
* treewide: Remove 'extern' from functions declarationElyes Haouas2023-05-261-9/+9
* soc/intel/meteorlake: Add B0 stepping CPU IDMusse Abdullahi2023-04-151-0/+1
* cpu/intel: Remove redefined SAPPHIRERAPIDS_SP CPUID to fix build errorJohnny Lin2023-03-241-6/+0
* soc/intel/xeon_sp: Report platform cpu infoNaresh Solanki2023-03-231-0/+9
* soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang2023-03-191-0/+6
* src: Move POST_BOOTBLOCK_CAR to common postcodes and use itMartin Roth2023-02-071-1/+0
* tree: Drop Intel Ice Lake supportFelix Singer2023-01-191-2/+0
* cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans2022-12-051-3/+5
* cpu/intel/car: Define post codesMartin Roth2022-11-231-0/+29
* mb/emulation/qemu-q35: Split smm_close() and smm_lock()Kyösti Mälkki2022-11-171-1/+2
* cpu/*: Drop PARALLEL_MP leftoversArthur Heymans2022-11-091-9/+0
* soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU IDJeremy Soller2022-09-161-1/+2
* include: Add SPDX-License-Identifiers to files missing themMartin Roth2022-08-011-0/+2
* soc/intel: Add Raptor Lake device IDszhixingma2022-06-281-0/+1
* cpu/intel/microcode: Have API to re-load microcode patchSubrata Banik2022-06-221-0/+4
* soc/intel/alderlake/report_platform.c: Add ADL-S identificationMichał Żygowski2022-06-171-0/+4
* mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEGArthur Heymans2022-06-011-0/+1
* soc/intel: Add Raptor Lake device IDsBora Guvendik2022-05-161-0/+2
* soc/intel/alderlake: Add new CPU IDLean Sheng Tan2022-04-041-0/+1
* soc/intel/alderlake: Update CPU IDs with correct steppingsLean Sheng Tan2022-04-041-4/+4
* soc/intel/common: Include Meteor Lake device IDsWonkyu Kim2022-03-091-1/+2
* soc/intel/common: Include Alder Lake-N device IDsUsha P2021-11-291-0/+1
* soc/intel/alderlake: Add CPU ID 0x906a4Meera Ravindranath2021-09-301-0/+1
* soc/intel: Add TGL-H CPUIDJeremy Soller2021-08-241-0/+1
* cpu/intel: Add dedicated file to grow Intel CPUIDsSubrata Banik2021-07-171-0/+57
* soc/intel/car: Add support for bootguard CARArthur Heymans2021-06-221-0/+3
* soc/intel/common: Add InSMM.STS supportAngel Pons2021-06-211-0/+2
* cpu/intel/msr.h: Sort MSRs in ascending orderAngel Pons2021-06-151-4/+4
* cpu/intel/msr.h: Add license headerAngel Pons2021-06-151-0/+2
* cpu/x86/entry16.S: Make Intel CBnT TOCTOU safeArthur Heymans2021-05-281-0/+10
* cpu/intel/microcode: Fix caching logic in intel_microcode_findFurquan Shaikh2021-03-121-1/+5
* cpu/intel/microcode: Fix typo in function parameterElyes HAOUAS2021-02-111-1/+1
* cpu/intel/microcode: Add caching layer in intel_microcode_findPatrick Rudolph2021-01-281-1/+3
* cpu/intel: add PC10 residency counter MSRMichael Niewöhner2021-01-071-0/+2
* cpu/intel/common: correct MSR for the Nominal Performance in CPPCMichael Niewöhner2020-10-311-0/+2
* cpu/intel/common: rework code previously moved to common cpu codeMichael Niewöhner2020-10-241-0/+1
* {cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner2020-10-241-0/+2
* {cpu,soc}/intel: replace AES-NI locking by common implemenation callMichael Niewöhner2020-10-211-0/+1
* cpu/intel/common: rework AES-NI lockingMichael Niewöhner2020-10-191-1/+1
* soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu codeMichael Niewöhner2020-10-191-0/+11
* src/include: Drop unneeded empty linesElyes HAOUAS2020-09-144-5/+0
* src/include: Add missing includesElyes HAOUAS2020-07-261-0/+2
* sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki2020-06-161-1/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-17 13:30:22 +0000